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| INTEGRATED CIRCUITS DATA SHEET P8xC591 Single-chip 8-bit microcontroller with CAN controller Objective Specification File under Integrated Circuits, IC20 1999 Aug 19 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller CONTENTS 1 1.1 1.2 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 8 9 10 11 11.1 11.2 11.3 12 12.1 12.2 12.3 12.4 12.5 13 14 14.1 14.2 14.3 14.4 14.5 15 15.1 15.2 15.3 16 16.1 FEATURES 80C51 Related Features of the 8xC591 CAN Related Features of the 8xC591 GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM FUNCTIONAL DIAGRAM PINNING INFORMATION Pinning diagram Pin description MEMORY ORGANIZATION Program Memory Addressing Expanded Data RAM addressing Dual DPTR I/O FACILITIES OSCILLATOR CHARACTERISTICS RESET LOW POWER MODES Stop Clock Mode Idle Mode Power-down Mode CAN, CONTROLLER AREA NETWORK Features of the PeliCAN Controller PeliCAN structure Communication between PeliCAN Controller and CPU Register and Message Buffer description CAN Registers SERIAL I/O SIO0 STANDARD SERIAL INTERFACE UART Multiprocessor Communications Serial Port Control Register Baud Rate Generation More about UART Modes Enhanced UART SIO1, I2C SERIAL IO Modes of Operation SIO1 Implementation and Operation Software Examples of SIO1 Service Routines TIMER 2 Features of Timer 2 17 18 18.1 18.2 18.3 19 20 20.1 20.2 20.3 20.4 20.5 21 21.1 21.2 21.3 21.4 22 22.1 23 24 25 25.1 26 26.1 26.2 27 28 28.1 29 30 WATCHDOG TIMER (T3) P8xC591 PULSE WIDTH MODULATED OUTPUTS Prescaler Frequency Control Register (PWMP) Pulse Width Register 0 (PWM0) Pulse Width Register 1 (PWM1) PORT 1 OPERATION ANALOG-TO-DIGITAL CONVERTER (ADC) ADC features ADC functional description 10-Bit Analog-to-Digital Conversion 10-Bit ADC Resolution and Analog Supply Power Reduction Modes INTERRUPTS Interrupt Enable Registers Interrupt Enable and Priority Registers Interrupt priority Interrupt Vectors INSTRUCTION SET Addressing Modes LIMITING VALUES DC CHARACTERISTICS (VALUES IN THIS TABLE NOT CONFIRMED) AC CHARACTERISTICS Timing symbol definitions EPROM CHARACTERISTICS Program verification Security bits PACKAGE OUTLINES SOLDERING Plastic leaded-chip carriers/quad flat-packs DEFINITIONS LIFE SUPPORT APPLICATIONS 1999 Aug 19 2 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 1 1.1 FEATURES 80C51 Related Features of the 8xC591 1.2 P8xC591 CAN Related Features of the 8xC591 * Full static 80C51 Central Processing Unit available as OTP, ROM and ROMless * 16 Kbytes internal Program Memory expandable externally to 64 Kbytes * 512 bytes on-chip Data RAM expandable externally to 64 Kbytes * Three 16-bit timers/counters T0, T1 (standard 80C51) and additional T2 (capture & compare) * 10-bit ADC with 6 multiplexed analog inputs with fast 8-bit ADC option * Two 8-bit resolution, Pulse Width Modulated outputs * 32 I/O port pins in the standard 80C51 pinout * I2C-bus serial I/O port with byte oriented master and slave functions * On-chip Watchdog Timer T3 * Extended temperature range: -40 to +85C * Accelerated (prescaler 1:1) instruction cycle time 375 ns @ 16 MHz * Operation voltage range: 5 V 10% * Security bits: - ROM version has 2 bits - OTP/EPROM version has 3 bits * 64 bytes Encryption array * 4 level priority interrupt, 15 interrupt sources * Full-duplex enhanced UART with programmable Baudrate Generator * Power Control Modes: - Clock can be stopped and resumed - Idle Mode - Power-down Mode * ADC active in Idle Mode * Second DPTR register * ALE inhibit for EMI reduction * Programmable I/O port pins (pseudo bi-directional, push-pull, high impedance, open drain) * Wake-up from Power-down by external interrupts * Software reset bit (AUXR1.5) * Low active reset pin * Power-on detect reset * Once mode * CAN 2.0B active controller, supporting 11-bit Standard and 29-bit Extended indentifiers * 1 Mbit/s CAN bus speed with 8 MHz clock achievable * 64 byte receive FIFO (can capture sequential Data Frames from the same source as required by the Transport Layer of higher protocols such as DeviceNet, CANopen and OSEK) * 13 byte transmit buffer * Enhanced PeliCAN core (from the SJA1000 stand-alone CAN2.0B controller) 1.2.1 PELICAN FEATURES * Four independently configurable Screeners (Acceptance Filters) * Each Screener has tow 32-bit specifiers: - 32-bit Match and - 32-bit Mask * 32-bits of Mask per Screener allows unique Group addressing per Screener * Higher layer protocols especially supported in Standard CAN format with: - Up to four, 11-bit ID Screeners that also Screen the two (2) Data Bytes - i.e., Data Frames are Screened by the CAN ID and by Data Byte content * Up to eight, 11-bit ID Screeners half of which also Screen the first Data Byte * All Screeners are changeable "on the fly" * Listen Only Mode, Self Test Mode * Error Code Capture, Arbitration Lost Capture, readable Error Counters 1999 Aug 19 3 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 2 GENERAL DESCRIPTION P8xC591 Hereafter these versions will be referred to as P8xC591. The temperature range includes (max. fCLK = 16 MHz): * -40 to +85 C version, for general applications The P8xC591 combines the functions of the P87C554 (microcontroller) and the SJA1000 (stand-alone CAN-controller) with the following enhanced features: * Enhanced CAN receive interrupt (level sensitive) * Extended acceptance filter * Acceptance filter changeable "on the fly". The main differences between P8xC591 and P87C554 are: * CAN-controller on chip * 6-input ADC * Low active Reset * 44 leads. The P8xC591 is a single-chip 8-bit-high-performance microcontroller, with on-chip CAN-controller, derived from the 80C51 microcontroller family. It uses the powerful 80C51 instruction set and includes the successful PeliCAN functionality of the SJA1000 CAN controller from Philips Semiconductors. The fully static core provides extended power save provisions as the oscillator can be stopped and easily restarted without loss of data. The improved internal clock prescaler of 1:1 achieves a 375 ns instruction cycle time at 16 MHz external clock rate. Figure 1 shows a Block Diagram of the P8xC591. The microcontroller is manufactured in an advanced CMOS process, and is designed for use in automotive and general industrial applications. In addition to the 80C51 standard features, the device provides a number of dedicated hardware functions for these applications. Three versions of the P8xC591 will be offered: * P80C591 (without ROM) * P83C591 (with ROM) * P87C591 (with OTP) 3 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME P80C591SFA P83C591SFA P87C591SFA P80C591SFB P83C591SFB P87C591SFB QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm PLCC44 plastic leaded chip carrier; 44 leads DESCRIPTION TEMPERATURE RANGE (C) VERSION SOT187-2 -40 to +85 SOT307-2 1999 Aug 19 4 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 4 BLOCK DIAGRAM P8xC591 INT0 INT1 T0 T1 PSEN RD EA ALE WR handbook, full pagewidth AVref+ AVSS AN0 to 5 PWM0 PWM1 RXD TXD 80C51 CONFIGURABLE CORE A0 to A7 CPU CORE TWO 16-BIT TIMER/EVENT COUNTERS (T0/T1) 16 KBYTES PROGRAM MEMORY 512 BYTES ADC DATA MEMORY PWM UART P8xC591 VDD VSS XTAL1 OSCILLATOR XTAL2 WATCHDOG TIMER (T3) PARALLEL I/O PORTS CPU INTERFACE (SFRs) 16-BIT TIMER/EVENT COUNTER WITH CAPTURE (T2) I2C SERIAL INTERFACE CAN 2.0 B INTERFACE RST P0 P1 P2 P3 RT2 T2 CT0x/INTx CMSR0 to 5 CMT0 to 1 SDA SCL TXDC RXDC MHI001 Fig.1 Block diagram P8xC591. 1999 Aug 19 5 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 5 FUNCTIONAL DIAGRAM P8xC591 handbook, full pagewidth VDD XTAL1 VSS alternative functions XTAL2 RST EA PSEN ALE 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 PORT 0 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 RXDC TXDC ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 and data bus low order address CAN CT0I/INT2 CT1I/INT3 CT2I/INT4 CT3I/INT5 SCL I2C SDA PORT 1 AVref+ AVSS PWM0 P8xC591 (44-PIN) PWM1 T2 RT2 CSMR0 CSMR1 CSMR2 CSMR3 RXD TXD INT0 INT1 T0 T1 WR RD 0 1 2 3 4 5 6 7 MHI002 PORT 3 0 1 2 3 4 5 6 7 PORT 2 address bus Fig.2 Functional diagram. 1999 Aug 19 6 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 6 6.1 PINNING INFORMATION Pinning diagram P8xC591 6 P1.4/ADC2/INT4/CT2I 5 P1.3/ADC1/INT3/CT1I 4 P1.2/ADC0/INT2/CT0I 2 P1.0/RXDC 3 P1.1/TXDC 43 P0.0/AD0 42 P0.1/AD1 41 P0.2/AD2 handbook, full pagewidth CT3I/INT5/ADC3/P1.5 SCL/ADC4/P1.6 SDA/ADC5/P1.7 7 8 9 40 P0.3/AD3 44 AVref+ 1 AVSS 39 P0.4/AD4 38 P0.5/AD5 37 P0.6/AD6 36 P0.7/AD7 35 EA/VPP RST 10 T2/P3.0/RXD 11 PWM0 12 RT2/P3.1/TXD 13 CMSR0/P3.2/INT0 14 CMSR1/P3.3/INT1 15 CMSR2/P3.4/T0 16 CMSR3/P3.5/T1 17 P8xC591 34 PWM1 33 ALE/PROG 32 PSEN 31 P2.7/A15 30 P2.6/A14 29 P2.5/A13 P3.6/WR 18 P3.7/RD 19 XTAL2 20 XTAL1 21 VSS 22 VDD 23 P2.0/A8 24 P2.1/A9 25 P2.2/A10 26 P2.3/A11 27 P2.4/A12 28 MHI003 Fig.3 Pinning Diagram for 44-lead LCC Package. 1999 Aug 19 7 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 44 P1.4/ADC2/INT4/CT2I 43 P1.3/ADC1/INT3/CT1I handbook, full pagewidth 42 P1.2/ADC0/INT2/CT0I 40 P1.0/RXDC 41 P1.1/TXDC 37 P0.0/AD0 36 P0.1/AD1 35 P0.2/AD2 P1.5/ADC3/INT5/CT3I P1.6/ADC4/SCL P1.7/ADC5/SDA RST P3.0/T2/RXD PWM0 RT2/P3.1/TXD CMSR0/P3.2/INT0 CMSR1/P3.3/INT1 1 2 3 4 5 6 7 8 9 34 P0.3/AD3 38 AVref+ 39 AVSS 33 P0.4/AD4 32 P0.5/AD5 31 P0.6/AD6 30 P0.7/AD7 29 EA/VPP P8xC591 28 PWM1 27 ALE/PROG 26 PSEN 25 P2.7/A15 24 P2.6/A14 23 P2.5/A13 CMSR2/P3.4/T0 10 CMSR3/P3.5/T1 11 P3.6/WR 12 P3.7/RD 13 XTAL2 14 XTAL1 15 VSS 16 VDD 17 P2.0/A8 18 P2.1/A9 19 P2.2/A10 20 P2.3/A11 21 P2.4/A12 22 MHI004 Fig.4 Pinning Diagram for 44-lead Plastic Quad Flat Package (QFP). 1999 Aug 19 8 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 6.2 Pin description Pin description for QFP44/PLCC44, see Note 1. PIN SYMBOL QFP44 RST P3.0to P3.7 4 PLCC44 10 DESCRIPTION P8xC591 Table 1 Reset: A Input to reset the P8xC591. It also provides a reset pulse as output when Timer T3 overflows. Port 3 (P3.0 to P3.7): 8-bit programmable I/O port lines; Port 3 can sink/source 4 LSTTL inputs. Port 3 pins serve alternate functions as follows: P3.0/RXD P3.1/TXD 5 7 11 13 14 15 16 17 18 19 RXD: Serial input port for UART; T2: T2 event input TXD: Serial output port for UART; RT2: T2 timer reset signal. Rising edge triggered. INT0: External interrupt input 0; CMSR0: Compare and Set/Reset output for Timer T2. INT1: External interrupt input 1; CMSR1: Compare and Set/Reset output for Timer T2. T0: Timer 0 external interrupt input; CMSR2: Compare and Set/Reset output for Timer T2. T1: Timer 1 external interrupt input; CMSR3: Compare and Set/Reset output for Timer T2. WR: External Data Memory Write strobe; RD: External Data Memory Read strobe. During reset, Port 3 will be asynchronously driven resistive HIGH. Port 3 has four modes selected on a per bit basis by writing to the P3M1 and P3M2 registers as follows: P3M1.x P3M2.x Mode Description 0 0 Pseudo-bidirectional (standard c51 configuration default) 0 1 Push-Pull 1 0 High impedance 1 1 Open drain P3.2/INT0/CMSR0 8 P3.3/INT1/ CMSR1 P3.4/T0/CMSR2 P3.5/T1/CMSR3 P3.6/WR P3.7/RD 9 10 11 12 13 XTAL2 XTAL1 14 15 20 21 Crystal pin 2: output of the inverting amplifier that forms the oscillator. Left open-circuit when an external oscillator clock is used. Crystal pin 1: input to the inverting amplifier that forms the oscillator, and input to the internal clock generator. Receives the external oscillator clock signal when an external oscillator is used. Ground; circuit ground potential. Power supply; power supply pin during normal operation and power reduction modes. VSS VDD 16 17 22 23 1999 Aug 19 9 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 PIN SYMBOL QFP44 P2.0/A08 to P2.7/A15 PLCC44 DESCRIPTION 18 to 25 24 to 31 Port 2 (P2.0 to P2.7): 8-bit programmable I/O port lines; A08 to A15: High-order address byte for external memory. Alternate function: High-order address byte for external memory (A08-A15). Port 2 is also used to input the upper order address during EPROM programming and verification. A8 is on P2.0, A9 on P2.1, through A12 on P2.4. During reset, Port 2 will be asynchronously driven HIGH. Port 2 has four output modes selected on a per bit basis by writing to the P2M1 and P2M2 registers as follows: P2M1.x P2M2.x Mode Description 0 0 Pseudo-bidirectional (standard c51 configuration default) 0 1 Push-Pull 1 0 High impedance 1 1 Open drain PSEN 26 32 Program Store Enable output: read strobe to the external Program Memory via Ports 0 and 2. Is activated twice each machine cycle during fetches from external Program Memory. When executing out of external Program Memory two activations of PSEN are skipped during each access to external Data Memory. PSEN is not activated (remains HIGH) during no fetches from external Program Memory. PSEN can sink/source 8 LSTTL inputs. It can drive CMOS inputs without external pull-ups. Address Latch Enable output. Latches the low byte of the address during access of external memory in normal operation. It is activated every six oscillator periods except during an external Data Memory access. ALE can sink/source 8 LSTTL inputs. It can drive CMOS inputs without an external pull-up. To prohibit the toggling of ALE pin (RFI noise reduction) the bit A0 (SFR: AUXR.0) must be set by software; see Table 4. PROG: the programming pulse input; alternative function for the P87C591. External Access input. If, during reset, EA is held at a TTL level HIGH the CPU executes out of the internal Program Memory. If, during reset, EA is held at a TTL level LOW the CPU executes out of external Program Memory via Port 0 and Port 2. EA is not allowed to float. EA is latched during reset and don't care after reset. VPP: the programming supply voltage; alternative function for the P87C591. ALE/PROG 27 33 EA/VPP 29 35 P0.0/AD0 to P0.7/AD7 30 to 37 36 to 43 Port 0: 8-bit open-drain bidirectional I/O port. During reset, Port 0 is HIGH-Impedance (Tri-State). AD7 to AD0: Multiplexed Low-order address and Data bus for external memory. During these accesses internal pull-ups are activated. Port 0 can sink/source up to 8 LSTTL inputs. AVref+ AVSS 38 39 44 1 Analog to Digital Conversion Reference Resistor: High-end. Analog ground. 1999 Aug 19 10 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 PIN SYMBOL QFP44 P1.0 to P1.4 P1.5 to P1.7 PLCC44 Port 1: 8-bit I/O port with a user configurable output type. The operation of Port 1 pins as inputs or outputs depends upon the port configuration selected. Each port pin is configured independently. Port 1 also provides various special functions as described below: P1.0 P1.1 40 41 2 3 RXDC: CAN Receiver input line. TXDC: CAN Transmit output line. During reset, Port P1.0 and P1.1 will be asynchronously driven resistive HIGH, P1.2 to P1.7 is High-Impedance (Tri-state). CT0I/INT2 / CT1I/INT3 / CT2I/INT4: T2 Capture timer inputs or External Interrupt inputs. ADC0 to ADC2: Alternate function: Input channels to ADC. P1.5 to P1.7 P1.5 P1.6 P1.7 1 to 3 1 2 3 7 to 9 7 8 9 ADC3 to ADC5: Input channels to ADC: CT3I/INT5: T2 Capture timer input or External Interrupt inputs. SCL: Serial port clock line I2C. SDA: Serial data clock line I2C. Port 1 has four modes selected on a per bit basis by writing to the P1M1 and P1M2 registers as follows: P1M1.x P1M2.x Mode Description 0 0 Pseudo-bidirectional (standard c51 configuration default (2)) 0 1 Push-Pull (2) 1 0 High impedance 1 1 Open drain Port 1 is also used to input the lower order address byte during EPROM programming and verification. A0 is on P1.0, etc. PWM0 PWM1 Notes 1. To avoid "latch-up" effect as power-on, the voltage on any pin at any time must not be higher or lower than VDD +0.5 V or VSS -0.5 V. 2. Not implemented for P1.6 and P1.7. 6 28 12 34 Pulse Width Modulation: Output 0. Pulse Width Modulation: Output 1. 40 to 44 2 to 6 1 to 3 7 to 9 DESCRIPTION P1.2 to P1.4 42 to 44 4 to 6 1999 Aug 19 11 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 7 MEMORY ORGANIZATION P8xC591 The Central Processing Unit (CPU) manipulates operands in three memory spaces as follows (see Fig.5): * 16 kbytes internal resp. 64 kbytes external Program Memory * 512 bytes internal Data Memory Main-and Auxiliary RAM * up to 64 kbytes external Data Memory (with 256 bytes residing in the internal Auxiliary RAM). handbook, full pagewidth 64K 64K EXTERNAL 16384 16383 OVERLAPPED SPACE 256 INTERNAL (EA = 1) EXTERNAL (EA = 0) 127 DIRECT AND INDIRECT 255 INDIRECT ONLY SFRs AUXILIARY RAM (EXTRAM = 0) 0 0 MAIN RAM PROGRAM MEMORY INTERNAL DATA MEMORY MHI005 EXTERNAL DATA MEMORY Fig.5 Memory map and address space with EXTRAM = 0. 1999 Aug 19 12 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 7.1 Program Memory P8xC591 The P8xC591 contains 16 Kbytes of on-chip Program Memory which can be extended to 64 Kbytes with external memories. When EA pin is held HIGH, the P8xC591 fetches instructions from internal ROM unless the address exceeds 3FFFh. Locations 4000h to FFFFh are fetched from external Program Memory. When the EA pin is held LOW, all instruction fetches are from external memory. The EA pin is latched during reset and is "don't care" after reset. Both, for the ROM and EPROM version of the P8xC591, precautions are implemented to protect the device against illegal Program Memory code reading. 7.2 Addressing means they have the same address, but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the CPU knows whether the access is to the upper 128 bytes of data RAM or to SFR space by the addressing mode used in the instruction. Instructions that use direct addressing access SFR space. For example: MOV 0A0H,#data accesses the SFR at location 0A0H (which is P2). Instructions that use indirect addressing access the Upper 128 bytes of data RAM. For example: MOV @ R0,#data where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H). The AUX-RAM can be accessed by indirect addressing, with EXTRAM bit cleared and MOVX instructions. This part of memory is physically located on-chip, logically occupies the first 256-bytes of external data memory. With EXTRAM = 0, the AUX-RAM is indirectly addressed, using the MOVX instruction in combination with any of the registers R0, R1 of the selected bank or DPTR. An access to AUX-RAM will not affect ports P0, P3.6 (WR#) and P3.7 (RD#). P2 SFR is output during external addressing. For example, with EXTRAM = 0, MOV @ R0,#data where R0 contains 0A0h, access the AUX-RAM at address 0A0H rather than external memory. An access to external data memory locations higher than FFH (i.e., 0100H to FFFFH) will be performed with the MOVX DPTR instructions in the same way as in the standard 80C51, so with P0 and P2 as data/address bus, and P3.6 and P3.7 as write and read timing signals. Refer to Table 4. With EXTRAM = 1, MOVX @ Ri and MOVX @ DPTR will be similar to the standard 80C51. MOVX @ Ri will provide an 8-bit address multiplexed with data on Port 0 and any output port pins can be used to output higher order address bits. This is to provide the external paging capability. MOVX @ DPTR will generate a 16-bit address. Port 2 outputs the high-order eight address bits (the contents of DPH) while Port 0 multiplexes the low-order eight address bits (DPL) with data. MOVX @ Ri and MOVX @ DPTR will generate either read or write signals on P3.6 (#WR) and P3.7 (#RD). The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM) internal data memory. The stack cannot be located in the AUX-RAM. 13 The P8xC591 has five methods for addressing the Program and Data memory: * Register * Direct * Register-Indirect * Immediate * Base-Register plus Index-Register-Indirect. For more details about Addressing modes please refer to Section 22.1 "Addressing Modes". 7.3 Expanded Data RAM addressing The P8xC591 has internal data memory that is mapped into four separate segments: the lower 128 bytes of RAM, upper 128 bytes of RAM, 128 bytes Special Function Register (SFR), and 256 bytes Auxiliary RAM (AUX-RAM) as shown in Figure 5. The four segments are: 1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are directly and indirectly addressable (see Fig.6). 2. The Upper 128 bytes of RAM (addresses 80H to FFH) are indirectly addressable. 3. The Special Function Registers, SFRs, (addresses 80H to FFH) are directly addressable only. All these SFRs are described in Table 4. 4. The 256-bytes AUX-RAM (00H - FFH) are indirectly accessed by move external instruction, MOVX, and within the EXTRAM bit cleared, see Table 3. The Lower 128 bytes can be accessed by either direct or indirect addressing. The Upper 128 bytes can be accessed by indirect addressing only. The Upper 128 bytes occupy the same address space as the SFR. That 1999 Aug 19 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller Table 2 7 Table 3 BIT 7 to 3 2 AUX-RAM Page Register (address 8EH) 6 5 4 3 2 LVADC 1 EXTRAM P8xC591 0 AO Description of AUX-RAM bits SYMBOL - LVADC Reserved for future use; see Note 1. Enable A/D low voltage operation. LVADC 0 1 Operating Mode Turns off A/D charge pump. Turns on A/D charge pump. Required for operation below 4 V. Operating Mode Internal AUX-RAM (00H - FH) access using MOVX @ RI / @ DPTR. External data memory access. Operating Mode ALE is permitted at a constant rate of 1/6 the oscillator frequency. ALE is active only during a MOVX or MOVC instruction. FUNCTION 1 EXTRAM Internal/External RAM (00H - FFH) access using MOVX @ RI / @ DPTR EXTRAM 0 1 0 AO Disable/Enable ALE. AO 0 1 Notes 1. User software should not write `1's to reserved bits. These bits may be used in future 80C51 family products to invoke new features. In that case, the reset or inactive of the new bit will be 0, and its active value will be `1'. The value read from a reserved bit is indeterminate. 2. Reset value is `xxxxxx10B'. 1999 Aug 19 14 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 handbook, full pagewidth 7Fh (MSB) (LSB) 127 2Fh 2Eh 2Dh 2Ch 2Bh 2Ah 29h 28h 27h 26h 25h 24h 23h 22h 21h 20h 1Fh 18h 17h 10h 0Fh 08h 07h 00h 7F 77 6F 67 5F 57 4F 47 3F 37 2F 27 1F 17 0F 07 7E 76 6E 66 5E 56 4E 46 3E 36 2E 26 1E 16 0E 06 7D 75 6D 65 5D 55 4D 45 3D 35 2D 25 1D 15 0D 05 7C 74 6C 64 5C 54 4C 44 3C 34 2C 24 1C 14 0C 04 7B 73 6B 63 5B 53 4B 43 3B 33 2B 23 1B 13 0B 03 7A 72 6A 62 5A 52 4A 42 3A 32 2A 22 1A 12 0A 02 79 71 69 61 59 51 49 41 39 31 29 21 19 11 09 01 78 70 68 60 58 50 48 40 38 30 28 20 18 10 08 00 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 24 23 16 15 8 7 0 REGISTER BANK 3 REGISTER BANK 2 REGISTER BANK 1 REGISTER BANK 0 MHI006 Fig.6 Internal Main RAM bit addresses. 1999 Aug 19 15 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 7.3.1 SPECIAL FUNCTION REGISTERS P8xC591 Table 4 Special Function Register Bit Address, Symbol or Alternate Port Function * = SFRs are bit addressable; # = SFRs are modified from or added to the 80C51 SFRs. NAME ACC* ADCH# ADCON# AUXR AUXR1 B* CTCON# CTH3# CTH2# CTH1# CTH0# CMH2# CMH1# CMH0# CTL3# CTL2# CTL1# CTL0# CML2# CML1# CML0# DPTR: DPH DPL DESCRIPTION Accumulator A/D converter high A/D control Auxiliary Auxiliary B register Capture control Capture high 3 Capture high 2 Capture high 1 Capture high 0 Compare high 2 Compare high 1 Compare high 0 Capture low 3 Capture low 2 Capture low 1 Capture low 0 Compare low 2 Compare low 1 Compare low 0 Data Pointer (2 bytes): Data Pointer High Data Pointer Low SFR ADDR E0H C6H C5H 8EH A2H F0H EBH CFH CEH CDH CCH CBH CAH C9H AFH AEH ADh ACH ABH AAH A9H BIT FUNCTIONS AND ADDRESSES MSB E7 E6 E5 E4 E3 E2 E1 LSB E0 RESET VALUE 00H xxxxxxxxb ADC.1 ADC8 F7 CTN3 ADC.0 AIDL F6 CTP3 SRST F5 CTN2 ADCI WDE F4 CTP2 ADCS WUPD F3 CTN1 AADR2 LVADC 0 F2 CTP1 AADR1 EXTRAM F1 CTN0 AADR0 A0 DPS F0 CTP0 xx000000b xxxxx110B 000000x0B 00H 00H xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB 00H 00H 00H xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB 00H 00H 00H 83h 82h AF AE EAD EE ECAN BE PAD FE PADH PCAN PCANH AD ES1 ED ECM1 BD PS1 FD PS1H PCM1 PCM1H AC ES0 EC ECM0 BC PS0 FC PS0H PCM0 PCM0H AB ET1 EB ECT3 BB PT1 FB PT1H PCT3 PCT3H AA EX1 EA ECT2 BA PX1 FA PX1H PCT2 PCT2H A9 ET0 E9 ECT1 B9 PT0 F9 PT0H PCT1 PCT1H A8 EX0 E8 ECT0 B8 PX0 F8 PX0H PCT0 PCT0H 00H 00H IENO*# Interrupt Enable 0 A8H EA EF 00H IEN1*# Interrupt Enable 1 E8H ET2 BF 00H IP0*# Interrupt Priority 0 B8H FF x0000000B IP0H IP1*# IP1H CANMOD CANCON CANDAT CANADR Interrupt Priority 0 high Interrupt Priority 1 Interrupt Priority 1 high CAN Mode Register CAN Command (w) and Interrupt (r) CAN Data CAN Address B7H F8h F7H C4H C3H C2H C1H PT2 PT2H x0000000B 00H 00H 00H 00H 00H 00H C7 CANSTA CAN Status (r) CAN Interrupt Enable (w) C0H BS BEIE C6 ES ALIE C5 TS EPIE C4 RS WUIE C3 TCS DOIE C2 TBS EIE C1 DOS TIE C0 RBS RIE 00H 1999 Aug 19 16 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 NAME P1M1 P1M2 P2M1 P2M2 P3M1 P3M2 DESCRIPTION Port 1 output mode 1 Port 1 output mode 2 Port 2 output mode 1 Port 2 output mode 2 Port 3 output mode 1 Port 3 output mode 2 SFR ADDR 92H 93H 94H 95H 9AH 9BH BIT FUNCTIONS AND ADDRESSES MSB LSB RESET VALUE FCH 00H 00H 00H 00H 00H B7 P3* Port 3 B0H RD A7 P2* Port 2 A0H A15 97 ADC5 P1* Port 1 90H SDA 87 P0* PCON PSW PWMP# PWMP1# PWMP0# RTE# S0ADDR S0ADEN SP S0BUF S0PSL S0PSH Port 0 Power Control Program Status Word PWM Prescaler PWM Register 1 PWM Register 0 Reset Enable Serial 0 Slave Address Slave Address Mask Stack Pointer Serial 0 Data Buffer Prescaler Value UART Prescaler/Value UART 80H 87H D0H FEH FDH FCH EFH CBh F9H 81H 99H FAH FBH SPS 9F S0CON* S1CON#* S1ADR# S1DAT# S1STA# Serial 0 Control Serial 1Control Serial 1 Address Serial 1 Data Serial 1 Status 98H D8H DBH DAH D9H SC4 DF STE# TH1 TH0 TL1 TL0 TMH2# TML2# Set Enable Timer High 1 Timer High 0 Timer Low 1 Timer Low 0 Timer High 2 Timer Low 2 EEH 8DH 8CH 8BH 8AH EDH ECH SM0/FE CR2 AD7 SMOD1 CY B6 WR A6 A14 96 ADC4 SCL 86 AD6 SMOD0 AC B5 CSMR3 T1 A5 A13 95 ADC3 CT3I 85 AD5 POF F0 B4 CSMR2 T0 A4 A12 94 ADC2 CT2I 84 AD4 WLE RS1 B3 CSMR1 INT1 A3 A11 93 ADC1 CT1I 83 AD3 GF1 RS0 B2 CSMR0 INT0 A2 A10 92 ADC0 CT0I 82 AD2 GF0 OV B1 RT2 TXD A1 A9 91 - TXDC 81 AD1 PD F1 B0 T2 RXD A0 A8 90 - RXDC 80 AD0 IDL P FFH 00x00000B 00H 00H 00H 00H FFH FFH FFH RP35 RP34 RP33 RP32 xxxx0000B 00H 00H 07H xxxxxxxxB 00H Prescaler higher nibble 9E SM1 ENS1 9D SM2 STA 9C REN ST0 SLAVE ADDRESS 9B TB8 SI 9A RB8 AA 99 TI CR1 98 RI CR0 GC 0xxx0000B 00H 00H 00H 00H SC3 DE SC2 DD SC1 DC SC0 DB SP35 0 DA SP34 0 D9 SP33 0 D8 SP32 F8H xxxx0000B 00H 00H 00H 00H 00H 00H 1999 Aug 19 17 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 NAME TMOD DESCRIPTION Timer Mode SFR ADDR 89H BIT FUNCTIONS AND ADDRESSES MSB GATE 8F C/T 8E TR1 T2IS0 CE CMI2/ CAN M1 8D TF0 T2ER CD CMI1 M0 8C TR0 T2B0 CC CMI0 GATE 8B IE1 T2P1 CB CTI3 C/T 8A IT1 T2P0 CA CTI2 M1 89 IE0 T2MS1 C9 CTI1 LSB M0 88 IT0 T2MS0 C8 CTI0 RESET VALUE 00H TCON* TM2CON# Timer Control Timer 2 Control 88H EAH TF1 T2IS1 CF 00H 00H TM2IR#* T3# Timer 2/CAN Int Flag Reg Timer 3 C8H FFH T2OV 00H 00H 1999 Aug 19 18 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 7.4 Dual DPTR P8xC591 INC DPTRIncrements the data pointer by 1 MCV DPTR, #data 16 constant MOV A, @ A+DPTR MOVX A, @ DPTR MOVX @ DPTR, A JMP @ A + DPTR Loads the DPTR with a 16-bit Move code byte relative to DPTR to ACC Move external RAM (16-bit address) to ACC Move ACC to external RAM (16-bit address) Jump indirect relative to DPTR The dual DPTR structure (see Figure 7) is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1/bit0 that allows the program code to switch between them. The DPS bit status should be saved by software when switching between DPTR0 and DPTR1. Note that bit 2 is not writable and is always read as a zero. This allows the DPS bit to be quickly toggled simply by executing an INC AUXR1 instruction without affecting the other bits. DPTR Instructions The instructions that refer to DPTR refer to the data pointer that is currently selected using the AUXR1/bit 0 register. The six instructions that use the DPTR are as follows: The data pointer can be accessed on a byte-by-byte basis by specifying the low or high byte in an instruction which accesses the SFRs. See application note AN458 for more details. handbook, full pagewidth DPS BT0 AUXR1 DPTR1 DPTR0 DPH (83H) DPL (82H) EXTERNAL DATA MEMORY MHI007 Fig.7 Dual DPTR: 1999 Aug 19 19 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 7.4.1 Table 5 7 ADC8 AUXR1 PAGE REGISTER AUXR1 Page Register (address A2H) 6 AIDL 5 SRST 4 WDE 3 WUPD 2 0 1 - P8xC591 0 DSP Table 6 Description of AUXR1 of bits User software should not write 1s to reserved bits. Theses bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be logic 0, and its active value will be logic 1. The value read from a reserved bit is indeterminate. The reset value of AUXR1 is (000000xB). BIT 7 SYMBOL ADC8 ADC8 0 1 6 5 4 3 2 1 0 AIDL SRST WDE WUPD 0 - DSP DESCRIPTION ADC Mode Switch. Switches between 10-bit conversion and 8-bit conversion Operating Mode 10-bit conversion (50 machine cycles) 8-bit conversion (24 machine cycles) Enables the ADC during Idle mode. Software Reset. Watchdog Timer Enable Flag. Enable Wake-up from Power-down. Reserved. Reserved. Data Pointer Switch. Switches between DPRT0 and DPTR1. ADC8 0 1 Operating Mode DPTR0 DPTR1 1999 Aug 19 20 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 8 I/O FACILITIES P8xC591 The P8xC591 consists of 32 I/O Port lines with partly multiple functions. The I/O's are held HIGH during reset (asynchronous, before oscillator is running). Ports 0, 1, 2 and 3 perform the following alternative functions: Port 0 is the same as in the 80C51. After reset the Port Special Function Register is set to 'FFh' as known from other 80C51 derivatives. Port 0 also provides the multiplexed low-order address and data bus used for expanding the P8xC591 with standard memories and peripherals. Port 1 supports several alternative functionalities. For this reason it has different I/O stages. Note, port P1.0 and P1.1 are Driven-High and P1.2 to P1.7 are High-Impedance (Tri-state) after reset. Port 2 is the same as in the 80C51. After reset the Port Special Function Register is set to 'FFh' as known from other 80C51 derivatives. Port 2 also provides the high-order address bus when the P8xC591 is expanded with external Program Memory and/or external Data Memory. Port 3 is the same as in the 80C51. During reset the Port 3 Special Function Register is set to 'FFh' as known from other 80C51 derivatives. 9 OSCILLATOR CHARACTERISTICS A pulse of such short duration is necessary in order to recover from a processor or system fault as fast as possible. Note that the short reset pulse from Timer T3 cannot discharge the power-on reset capacitor (see Figure 8). Consequently, when the watchdog timer is also used to set external devices, this capacitor arrangement should not be connected to the RST pin, and a different circuit should be used to perform the power-on reset operation. A timer T3 overflow, if enabled, will force a reset condition to the P8xC591 by an internal connection, whether the output RST is pulled-up HIGH or not. A reset may be performed in software by setting the software reset bit, SRST (AUXR1.5). This device also has a Power-on Detect Reset circuit as VCC transitions from VCC past VRST. handbook, halfpage VDD SCHMITT TRIGGER RESET CIRCUITRY on-chip resistor RST overflow timer T3 MHI008 XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator, as shown in the logic symbol. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal. However, minimum and maximum high and low times specified in the data sheet must be observed. 10 RESET A reset is accomplished by holding the RST pin LOW for at least two machine cycles (12 oscillator periods), while the oscillator is running. To insure a good power-on reset, the RST pin must be low long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. The RST line can also be pulled LOW internally by a pull-down transistor activated by the watchdog timer T3. The length of the output pulse from T3 is 3 machine cycles. Fig.8 On-Chip Reset Configuration. handbook, halfpage VDD RRST RST 2.2 F P8xC591 MHI009 Fig.9 Power-on Reset. 1999 Aug 19 21 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 11 LOW POWER MODES 11.1 Stop Clock Mode 11.3 Power-down Mode P8xC591 The static design enables the clock speed to be reduced down to 0 MHz (stopped). When the oscillator is stopped, the RAM and Special Function Registers retain their values. This mode allows step-by-step utilization and permits reduced system power consumption by lowering the clock frequency down to any value. For lowest power consumption the Power-down mode is suggested. 11.2 Idle Mode To save even more power, a Power-down mode (see Table 7) can be invoked by software. In this mode, the oscillator is stopped and the instruction that invoked Power Down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values down to 2.0 V and care must be taken to return VCC to the minimum specified operating voltages before the Power-down Mode is terminated. A hardware reset or external interrupt can be used to exit from Power-down. The Wake-up from Power-down bit, WUPD (AUXR1.3) must be set in order for an interrupt to cause a Wake-up from Power-down. Reset redefines all the SFRs but does not change the on-chip RAM. A Wake-up allows both the SFRs and the on-chip RAM to retain their values. To properly terminate Power-down the reset or external interrupt should not be executed before VCC is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize (normally less than 10 ms). In the Idle mode (see Table 7), the CPU puts itself to sleep while all of the on-chip peripherals stay active. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the Idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode. The Idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a Power-on reset. Table 7 Status of external pins during Idle and Power-down modes MEMORY internal external internal external ALE 1 1 0 0 PSEN 1 1 0 0 PORT 0 port data float port data float PORT 1 port data port data port data port data PORT 2 port data address port data port data PORT 3 port data port data port data port data PWM0/ PWM1 high high high high MODE Idle Power-down With an external interrupt, INT0 and INT1 must be enabled and configured as level-sensitive. Holding the pin low restarts the oscillator but bringing the pin back high completes the exit. Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction that put the device into Power-down. 1999 Aug 19 22 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 11.3.1 POWER OFF FLAG 11.3.3 ONCETM MODE P8xC591 The Power Off Flag (POF) is set by on-chip circuitry when the VCC level on the P8xC591 rises from 0 to 5 V. The POF bit can be set or cleared by software allowing a user to determine if the reset is the result of a power-on or warm after Power-down. The VCC level must remain above 3 V for the POF to remain unaffected by the VCC level. 11.3.2 DESIGN CONSIDERATION The ONCETM ("On-Circuit Emulation") Mode facilities testing and debugging of systems without the device having to be removed from the circuit. The ONCE Mode is invoked by: 1. Pull ALE low while the device is in reset an PSEN is high, 2. Hold ALE low as RST is deactivated. While the device is in ONCE Mode, the Port 0 pins go into a float state, and the other port pins and ALE and PSEN are weakly pulled high. The oscillator circuit remains active. While the device is in this mode, an emulator or test CPU can be used to drive the circuit. Normal operation is restored when a normal reset is applied. 11.3.4 REDUCED EMI MODE * When the Idle mode is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. The ALE-Off bit, AO (AUXR.0) can be set to 0 disable the ALE output. It will automatically become active when required for external memory accesses and resume to the OFF state after completing the external memory access. 11.3.5 Table 8 7 POWER CONTROL REGISTER (PCON) Power Control Register (address 87H) 6 SMOD0 5 POF 4 WLE 3 GF1 2 GF0 1 PD 0 IDL SMOD1 Table 9 Description of PCON bits If logic 1s are written to PD and IDL at the same time, PD takes precedence. The reset value of PCON is (0XX00000). BIT 7 6 5 4 3 2 1 0 SYMBOL SMOD1 SMOD0 POF WLE GF1 GF0 PD IDL Power-down mode select. Setting this bit activates Power-down mode. It can only be set if the Watchdog timer enable bit `WDE' is set to logic 0. Idle mode select. Setting this bit activates the Idle mode. DESCRIPTION Double Baud rate. When set to logic 1 the baud rate is doubled when the serial port SIO0 is being used in Modes 1, 2 and 3. Double Baud rate. Selects SM0/FE for SCON.7 bit. Power Off flag. Watchdog Load Enable. This flag must be set by software prior to loading T3 (Watchdog Timer). It is cleared when T3 is loaded. General purpose flag bits. 1999 Aug 19 23 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 12 CAN, CONTROLLER AREA NETWORK Controller Area Network is the definition of a high performance communication protocol for serial data communication. The CAN controller circuitry is designed to provide a full implementation of the CAN-Protocol according to the CAN Specification Version 2.0 B. Microcontroller including this on-chip CAN Controller are used to build powerful local networks, both for general industrial and automotive environments. The result is a strongly reduced wiring harness and enhanced diagnostic and supervisory capabilities. The P8xC591 includes the same functions known from the SJA1000 stand-alone CAN Controller from Philips Semiconductors with the following improvements: * Enhanced receive interrupt * Enhanced acceptance filter - 8 filter for standard frame formats - 4 filter for extended formats - "change on the fly" feature. 12.1 12.1.1 Features of the PeliCAN Controller GENERAL CAN FEATURES 12.1.2 P8xC591 P8XC591 PELICAN FEATURES (ADDITIONAL TO CAN 2.0B) * Supports 11-bit identifier as well as 29-bit identifier * Bit rates up to 1 Mbit/s * Error Counters with read / write access * Programmable Error Warning Limit * Arbitration Lost Interrupt with detailed bit position * Single Shot Transmission (no re-transmission) * Listen Only Mode (no acknowledge, no active error flags) * Hot Plugging support (software driven bit rate detection) * Extended receive buffer (FIFO, 64 byte) * Receive Buffer level sensitive Receive Interrupt * High Priority Acceptance Filters for Receive Interrupt * Acceptance Filters with "change on the fly" feature * Reception of "own" messages (Self Reception Request) * Programmable CAN output driver configuration * CAN 2.0B protocol compatibility * Multi-master architecture * Bus access priority determined by the message identifier (11 bit or 29 bit) * Non destructive bit-wise arbitration * Guaranteed latency time for high priority messages * Programmable transfer rate (up to 1Mbit/s) * Multicast and broadcast message facility * Data length from 0 up to 8 bytes * Powerful error handling capability * Non-return-to-zero (NRZ) coding/decoding with bit-stuffing * Suitable for use in a wide range of networks including SAE's network classes A, B, C. 1999 Aug 19 24 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 12.2 PeliCAN structure P8xC591 A 80C51 CPU Interface connects the PeliCAN to the internal bus of the P8xC591 microcontroller. Via five Special Function Registers CANADR, CANDAT, CANMOD, CANSTA and CANCON the CPU has access to the PeliCAN. The SFR will described later on. handbook, full pagewidth control address/data INTERFACE MANAGEMENT LOGIC MESSAGE BUFFER TRANSMIT BUFFER PeliCAN Core Block ERROR MANAGEMENT LOGIC TXDC TX BIT TIMING LOGIC BIT STREAM PROCESSOR MHI010 RECEIVE FIFO TRANSMIT MANAGEMENT LOGIC RXDC RX ACCEPTANCE FILTER Fig.10 Block Diagram of the PeliCAN. 1999 Aug 19 25 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 12.2.1 INTERFACE MANAGEMENT LOGIC (IML) 12.2.7 BIT TIMING LOGIC (BTL) P8xC591 The Interface Management Logic interprets commands from the CPU, controls addressing of the CAN Registers and provides interrupts and status information to the CPU. Additionally it drives the universal interface of the PeliCAN. 12.2.2 TRANSMIT BUFFER (TXB) The Transmit Buffer is an interface between the CPU and the Bit Stream Processor (BSP) and is able to store a complete CAN message which should be transmitted over the CAN network. The buffer is 13 bytes long, written by the CPU and read out by the BSP or the CPU itself. 12.2.3 RECEIVE BUFFER (RXB, RXFIFO) The Bit Timing Logic monitors the serial CAN bus line and handles the Bus line-related bit timing. It synchronizes to the bit stream on the CAN Bus on a "recessive" to "dominant" Bus line transition at the beginning of a message (hard synchronization) and resynchronizes on further transitions during the reception of a message (soft synchronization). The BTL also provides programmable time segments to compensate for the propagation delay times and phase shifts (e.g., due to oscillator drifts) and to define the sampling time and the number of samples to be taken within a bit time. 12.2.8 TRANSMIT MANAGEMENT LOGIC (TML) The Receive Buffer is an interface between the Acceptance Filter and the CPU and stores the received and accepted messages from the CAN Bus line. The Receive Buffer (RXB) represents a CPU-accessible 13-byte-window of the Receive FIFO (RXFIFO), which has a total length of 64 bytes depending on the implementation. With the help of this FIFO the CPU is able to process one message while other messages are being received. 12.2.4 ACCEPTANCE FILTER (ACF) The Transmit Management Logic provides the driver signals for the push-pull CAN TX transistor stage. Depending on the programmable output driver configuration the external transistors are switched on or off. Additionally a short circuit protection and the asynchronous float on hardware reset is performed here. The Acceptance Filter compares the received identifier with the Acceptance Filter Table contents and decides whether this message should be accepted or not. In case of a positive acceptance test, the complete message is stored in the RXFIFO. The ACF contains 4 independent Acceptance Filter banks supporting extended and standard CAN frames with "change on the fly" feature. 12.2.5 BIT STREAM PROCESSOR (BSP) The Bit Stream Processor is a sequencer, controlling the data stream between the Transmit Buffer, RXFIFO and the CAN-Bus. It also performs the error detection, arbitration, stuffing and error handling on the CAN bus. 12.2.6 ERROR MANAGEMENT LOGIC (EML) The EML is responsible for the error confinement of the transfer-layer modules. It gets error announcements from the BSP and then informs the BSP and IML about error statistics. 1999 Aug 19 26 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 12.3 Communication between PeliCAN Controller and CPU P8xC591 A 80C51 CPU Interface connects the PeliCAN to the internal bus of an 80C51 microcontroller. Special Function Registers, allows a smart and fast access to the PeliCAN registers and RAM area. Because of the big address range to be supported, an indirect pointer based addressing is included allowing a fast register access with address autoincrement mode. This reduces the needed number of Special Function Registers to an amount of 5. * Five Special Function Registers (SFRs) * Register address generation in auto-increment mode * Access to the complete address range of the PeliCAN handbook, full pagewidth INTERFACE CANADR CANDAT read write CAN CONTROLLER SFRs CANCON 80C51 CORE data PeliCAN CANSTA address CANMOD MHI020 Fig.11 CPU to CAN Interfacing. 12.3.1 SPECIAL FUNCTION REGISTERS Via the five Special Function Registers CANADR, CANDAT, CANMOD, CANSTA and CANCON the CPU has access to the PeliCAN Block. Note that CANCON and CANSTA have different registers mapped depending on the direction of the access. The PeliCAN registers may be accessed in two different ways. The most important registers, which should support software polling or are controlling major CAN functions are accessible directly as separate SFRs. Other parts of the PeliCAN Block are accessible using an indirect pointer mechanism. In order to achieve a high data throughput even if the indirect access is used, an address auto-increment feature is included here. 1999 Aug 19 27 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller Table 10 CAN Special Function Registers SFR CANADR CANDAT CANMOD CANSTA ACCESS Read/ Write Read/ Write Read/ Write Read Write CANCON Read Write PELICAN REG. Mode Status Interrupt Enable Interrupt Command BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 P8xC591 BIT0 SFR ADDR C1 C2 C4 C0 CANA7 CANA6 CANA5 CANA4 CANA3 CANA2 CANA1 CANA0 CAND7 CAND6 CAND5 CAND4 CAND3 CAND2 CAND1 CAND0 TM BS BEIE BEI RIPM ES ALIE ALI RPM TS EPIE EPI SM RS WUIE WUI SRR - TCS DOIE DOI CDO STM TBS EIE EI RRB LOM DOS TIE TI AT RM RBS RIE RI TR C3 12.3.2 CANADR This read/write register defines the address of one of the PeliCAN internal registers to be accessed via CANDAT. It could be interpreted as a pointer to the PeliCAN. The read and write access to the PeliCAN Block register is performed using the CANDAT register. With the implemented auto address increment mode a fast stack-like reading and writing of CAN Controller internal registers is provided. IF the currently defined address within CANADR is above or equal to 32 decimal, the content of CANADR is incremented automatically after any read or write access to CANDAT. For instance, loading a message into the Transmit Buffer can be done by writing the first Transmit Buffer Address (112 decimal) into CANADR and then moving byte by byte of the message to CANDAT. Incrementing CANADR beyond FFh resets CANADR to 00h. In case CANADR is below 32 decimal, there is no automatic address incrementation performed. CANADR keeps its value even if CANDAT is accessed for reading or writing. This is to allow polling of registers in the lower address space of the PeliCAN Controller. 12.3.3 CANDAT REGISTER which is selected by CANADR. CANDAT is implemented as a read/write register. Note that any access to this register automatically increments CANADR if the current address within CANADR is above ore equal to 32 decimal. 12.3.4 CANMOD With a read or write access to CANMOD the Mode Register of the PeliCAN is accessed directly. The Mode register is located at address 00h within the PeliCAN Block. 12.3.5 CANSTA The CANSTA SFR provides a direct access to the Status Register of the PeliCAN as well as to the Interrupt Enable Register, depending on the direction of the access. Reading CANSTA is an access to the Status Register of the PeliCAN (address 2). When writing to CANSTA the Interrupt Enable Register is accessed (address 4). 12.3.6 CANCON CANDAT is implemented as a read/write register. The Special Function Register CANDAT appears as a port to the CAN Controller's internal register (memory location) being selected by CANADR. Reading or writing CANDAT is effectively an access to that PeliCAN internal register, The CANCON SFR provides a direct access to the Interrupt Register of the PeliCAN as well as to the Command register, depending on the direction of the access. When reading CANCON the Interrupt Register of the PeliCAN is accessed (address 3), while writing to CANCON means an access to the Command Register (address 01). 1999 Aug 19 28 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 12.4 12.4.1 Register and Message Buffer description ADDRESS LAYOUT P8xC591 The PeliCAN internal registers appear to the host CPU as on-chip memory mapped peripheral registers. Because the PeliCAN can operate in different modes (Operating / Reset, see also Mode Register), one have to distinguish between different internal address definitions. Starting from CAN Address 128 the complete internal FIFO RAM is mapped to the CPU Interface. Table 11 Address allocation CAN ADDR. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 to 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 B A N K 2 B A N K 1 Mode (00) Status Interrupt Interrupt Enable Rx Interrupt Level Bus Timing 0 Bus Timing 1 See Note 2 Rx Message Counter Rx Buffer Start Address Arbitration Lost Capture Error Code Capture Error Warning Limit Rx Error Counter TX Error Counter reserved (00) ACF Mode ACF Enable ACF Priority Acceptance Code 0 Acceptance Code 1 Acceptance Code 2 Acceptance Code 3 Acceptance Mask 0 Acceptance Mask 1 Acceptance Mask 2 Acceptance Mask 3 Acceptance Code 0 Acceptance Code 1 Acceptance Code 2 Acceptance Code 3 Acceptance Mask 0 Acceptance Mask 1 Acceptance Mask 2 Acceptance Mask 3 OPERATING MODE READ Mode Command Interrupt Enable Rx Interrupt Level Error Warning Limit ACF Enable ACF Priority Acceptance Code 0 Acceptance Code 1 Acceptance Code 2 Acceptance Code 3 Acceptance Mask 0 Acceptance Mask 1 Acceptance Mask 2 Acceptance Mask 3 Acceptance Code 0 Acceptance Code 1 Acceptance Code 2 Acceptance Code 3 Acceptance Mask 0 Acceptance Mask 1 Acceptance Mask 2 Acceptance Mask 3 RESET MODE WRITE Mode (00) Status Interrupt Interrupt Enable Rx Interrupt Level Bus Timing 0 Bus Timing 1 Rx Message Counter Rx Buffer Start Address Arbitration Lost Capture Error Code Capture Error Warning Limit Rx Error Counter TX Error Counter reserved (00) ACF Mode ACF Enable ACF Priority Acceptance Code 0 Acceptance Code 1 Acceptance Code 2 Acceptance Code 3 Acceptance Mask 0 Acceptance Mask 1 Acceptance Mask 2 Acceptance Mask 3 Acceptance Code 0 Acceptance Code 1 Acceptance Code 2 Acceptance Code 3 Acceptance Mask 0 Acceptance Mask 1 Acceptance Mask 2 Acceptance Mask 3 READ Mode Command - WRITE Interrupt Enable Rx Interrupt Level Bus Timing 0 Bus Timing 1 Error Warning Limit Rx Error Counter TX Error Counter ACF Mode ACF Enable ACF Priority Acceptance Code 0 Acceptance Code 1 Acceptance Code 2 Acceptance Code 3 Acceptance Mask 0 Acceptance Mask 1 Acceptance Mask 2 Acceptance Mask 3 Acceptance Code 0 Acceptance Code 1 Acceptance Code 2 Acceptance Code 3 Acceptance Mask 0 Acceptance Mask 1 Acceptance Mask 2 Acceptance Mask 3 1999 Aug 19 29 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller OPERATING MODE READ Acceptance Code 0 Acceptance Code 1 B A N K 3 Acceptance Code 2 Acceptance Code 3 Acceptance Mask 0 Acceptance Mask 1 Acceptance Mask 2 Acceptance Mask 3 Acceptance Code 0 Acceptance Code 1 B A N K 4 Acceptance Code 2 Acceptance Code 3 Acceptance Mask 0 Acceptance Mask 1 Acceptance Mask 2 Acceptance Mask 3 reserved (00) (SFF) 96 97 98 99 100 101 102 103 104 105 106 107 108 109 to 111 Rx Frame Info Rx Identifier 1 Rx Identifier 2 Rx Data 1 Rx Data 2 Rx Data 3 Rx Data 4 Rx Data 5 Rx Data 6 Rx Data 7 Rx Data 8 (FIFO RAM) (1) (FIFO RAM) (1) reserved (00) (SFF) 112 113 114 Tx Frame Info Tx Identifier 1 Tx Identifier 2 (EFF) Tx Frame Info Tx Identifier 1 Tx Identifier 2 Tx Frame Info Tx Identifier 1 Tx Identifier 2 Tx Frame Info Tx Identifier 1 Tx Identifier 2 (EFF) Rx Frame Info Rx Identifier 1 Rx Identifier 2 Rx Identifier 3 Rx Identifier 4 Rx Data 1 Rx Data 2 Rx Data 3 Rx Data 4 Rx Data 5 Rx Data 6 Rx Data 7 Rx Data 8 - P8xC591 RESET MODE CAN ADDR. 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 to 95 WRITE Acceptance Code 0 Acceptance Code 1 Acceptance Code 2 Acceptance Code 3 Acceptance Mask 0 Acceptance Mask 1 Acceptance Mask 2 Acceptance Mask 3 Acceptance Code 0 Acceptance Code 1 Acceptance Code 2 Acceptance Code 3 Acceptance Mask 0 Acceptance Mask 1 Acceptance Mask 2 Acceptance Mask 3 - READ Acceptance Code 0 Acceptance Code 1 Acceptance Code 2 Acceptance Code 3 Acceptance Mask 0 Acceptance Mask 1 Acceptance Mask 2 Acceptance Mask 3 Acceptance Code 0 Acceptance Code 1 Acceptance Code 2 Acceptance Code 3 Acceptance Mask 0 Acceptance Mask 1 Acceptance Mask 2 Acceptance Mask 3 reserved (00) (SFF) Rx Frame Info Rx Identifier 1 Rx Identifier 2 Rx Data 1 Rx Data 2 Rx Data 3 Rx Data 4 Rx Data 5 Rx Data 6 Rx Data 7 Rx Data 8 (FIFO RAM) (1) (FIFO RAM) (1) reserved (00) (SFF) Tx Frame Info Tx Identifier 1 Tx Identifier 2 (EFF) Tx Frame Info Tx Identifier 1 Tx Identifier 2 (EFF) Rx Frame Info Rx Identifier 1 Rx Identifier 2 Rx Identifier 3 Rx Identifier 4 Rx Data 1 Rx Data 2 Rx Data 3 Rx Data 4 Rx Data 5 Rx Data 6 Rx Data 7 Rx Data 8 WRITE Acceptance Code 0 Acceptance Code 1 Acceptance Code 2 Acceptance Code 3 Acceptance Mask 0 Acceptance Mask 1 Acceptance Mask 2 Acceptance Mask 3 Acceptance Code 0 Acceptance Code 1 Acceptance Code 2 Acceptance Code 3 Acceptance Mask 0 Acceptance Mask 1 Acceptance Mask 2 Acceptance Mask 3 (SFF) Rx Frame Info Rx Identifier 1 Rx Identifier 2 Rx Data 1 Rx Data 2 Rx Data 3 Rx Data 4 Rx Data 5 Rx Data 6 Rx Data 7 Rx Data 8 (FIFO RAM) (1) (FIFO RAM) (1) (SFF) Tx Frame Info Tx Identifier 1 Tx Identifier 2 (EFF) Tx Frame Info Tx Identifier 1 Tx Identifier 2 (EFF) Rx Frame Info Rx Identifier 1 Rx Identifier 2 Rx Identifier 3 Rx Identifier 4 Rx Data 1 Rx Data 2 Rx Data 3 Rx Data 4 Rx Data 5 Rx Data 6 Rx Data 7 Rx Data 8 1999 Aug 19 30 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 CAN ADDR. 115 116 117 118 119 120 121 122 123 124 125 to 127 128 ... 191 Tx Data 1 Tx Data 2 Tx Data 3 Tx Data 4 Tx Data 5 Tx Data 6 Tx Data 7 Tx Data 8 OPERATING MODE READ Tx Identifier 3 Tx Identifier 4 Tx Data 1 Tx Data 2 Tx Data 3 Tx Data 4 Tx Data 5 Tx Data 6 Tx Data 7 Tx Data 8 Tx Data 1 Tx Data 2 Tx Data 3 Tx Data 4 Tx Data 5 Tx Data 6 Tx Data 7 Tx Data 8 (TXB Memory) (TXB Memory) RESET MODE WRITE Tx Identifier 3 Tx Identifier 4 Tx Data 1 Tx Data 2 Tx Data 3 Tx Data 4 Tx Data 5 Tx Data 6 Tx Data 7 Tx Data 8 Tx Data 1 Tx Data 2 Tx Data 3 Tx Data 4 Tx Data 5 Tx Data 6 Tx Data 7 Tx Data 8 (TXB Memory) (TXB Memory) READ Tx Identifier 3 Tx Identifier 4 Tx Data 1 Tx Data 2 Tx Data 3 Tx Data 4 Tx Data 5 Tx Data 6 Tx Data 7 Tx Data 8 Tx Data 1 Tx Data 2 Tx Data 3 Tx Data 4 Tx Data 5 Tx Data 6 Tx Data 7 Tx Data 8 WRITE Tx Identifier 3 Tx Identifier 4 Tx Data 1 Tx Data 2 Tx Data 3 Tx Data 4 Tx Data 5 Tx Data 6 Tx Data 7 Tx Data 8 (TXB Memory) (TXB Memory) (TXB Memory) (TXB Memory) General purpose RAM Internal RAM Address 0 (FIFO) ... Internal RAM Address 63 (FIFO) General purpose RAM - General purpose RAM Internal RAM Address 0 (FIFO) ... Internal RAM Address 63 (FIFO) General purpose RAM Internal RAM Address 0 (FIFO) ... Internal RAM Address 63 (FIFO) Notes 1. These address locations reflect the FIFO RAM space behind the current message. The contents are randomly after power-up and contain the beginning of the next message that is received after the current one. If no further message is received, parts of old messages may occur here. 2. Register at address 8 performs NO system function; reserved for future use. 1999 Aug 19 31 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 12.5 12.5.1 CAN Registers RESET VALUES P8xC591 Detection of a set Reset Mode bit results in aborting the current transmission / reception of a message and entering the Reset Mode. On the `1'-to-'0' transition of the Reset Mode bit, the CAN Controller returns to the mode defined within the Mode Register. Table 12 Reset mode configuration "X" means that the values of these registers or bits are not influenced. ADDR. 0 REGISTER Mode BIT MOD.7 MOD.6 MOD.5 MOD.4 MOD.3 MOD.2 MOD.1 MOD.0 CMR.7-5 CMR.4 CMR.3 CMR.2 CMR.1 CMR.0 SR.7 SR.6 SR.5 SR.4 SR.3 SR.2 SR.1 SR.0 IR.7 IR.6 IR.5 IR.4 IR.3 IR.2 IR.1 IR.0 IER.7 IER.6 IER.5 IER.4 IER.3 IER.2 IER.1 IER.0 BTR0.7 BTR0.6 BTR0.5 BTR0.4 BTR0.3 BTR0.2 BTR0.1 BTR0.0 BTR1.7 BTR1.6 BTR1.5 BTR1.4 BTR1.3 BTR1.2 BTR1.1 BTR1.0 SYMBOL TM RIPM RPM SM STM LOM RM SRR CDO RRB AT TR BS ES TS RS TCS TBS DOS RBS BEI ALI EPI WUI DOI EI TI RI BEIE ALIE EPIE WUIE DOIE EIE TIE RIE RIL SJW.1 SJW.0 BRP.5 BRP.4 BRP.3 BRP.2 BRP.1 BRP.0 NAME Test Mode Receive Interrupt Pulse Mode Receive Polarity Mode Sleep Mode Self Test Mode Listen Only Mode Reset Mode Self Reception Request Clear Data Overrun Release Receive Buffer Abort Transmission Transmission Request Bus Status Error Status Transmit Status Receive Status Transmission Complete Status Transmit Buffer Status Data Overrun Status Receive Buffer Status Bus Error Interrupt Arbitration Lost Interrupt Error Passive Interrupt Wake-Up Interrupt Data Overrun Interrupt Error Warning Interrupt Transmit Interrupt Receive Interrupt Bus Error Interrupt Enable Arbitr. Lost Interrupt Enable Error Passive Interrupt Wake-Up Interrupt Enable Data Overrun Interrupt Enable Error Warning Interrupt Enable Transmit Interrupt Enable Receive Interrupt Enable Rx Interrupt Level Synchronization Jump Width 1 Synchronization Jump Width 0 Baud Rate Prescaler 5 Baud Rate Prescaler 4 Baud Rate Prescaler 3 Baud Rate Prescaler 2 Baud Rate Prescaler 1 Baud Rate Prescaler 0 Sampling Time Segment 2.2 Time Segment 2.1 Time Segment 2.0 Time Segment 1.3 Time Segment 1.2 Time Segment 1.1 Time Segment 1.0 0 X 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 X X X X X X X X RESET BY HARDWARE (disabled) no change (active low) (wake-up) (reserved) (normal) (normal) (present) (reserved) (absent) (no action) (no action) (absent) (absent) (Bus-On) (ok) (wait idle) (wait idle) (complete) (released) (absent) (empty) (reset) (reset) (reset) (reset) (reset) (reset) (reset) (reset) no change no change no change no change no change no change no change no change SETTING MOD.0 BY SOFTWARE OR DUE TO BUS-OFF 0 X 0 0 0 X X 1 0 0 0 0 0 0 0 0 0 0 0 X 0 0 X 0 0 0 0 X 0 0 X X X X X X X X (disabled) no change (active high) (wake-up) (reserved) no change no change (present) (reserved) (absent) (no action) (no action) (absent) (absent) (reset) (reset) (reset) (reset) (reset) no change (1) (reset) (reset) no change (1) (reset) (reset) (reset) (reset) no change (reset) (reset) no change no change no change no change no change no change no change no change 1 Command 2 Status 3 Interrupt 4 Interrupt Enable 5 6 Rx Interrupt Level Bus Timing 0 00000000b X X X X X X X X X X X X X X X X no change no change no change no change no change no change no change no change no change no change no change no change no change no change no change no change X no change X X X X X X X X X X X X X X X X no change no change no change no change no change no change no change no change no change no change no change no change no change no change no change no change 7 Bus Timing 1 SAM TSEG2.2 TSEG2.1 TSEG2.0 TSEG1.3 TSEG1.2 TSEG1.1 TSEG1.0 1999 Aug 19 32 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller RESET BY HARDWARE 0 00000000b 0 0 96d 0 (reset) 0 (reset) 0 0 0 0 0 0 0 0 X X X X X X X X X X X X X X X X (SFF) (dual) (SFF) (dual) (SFF) (dual) (SFF) (dual) no change no change no change no change no change no change no change no change no change no change no change no change no change no change no change no change P8xC591 SETTING MOD.0 BY SOFTWARE OR DUE TO BUS-OFF 0 X no change X no change X no change X no change X no change (2) X no change (2) X X X X X X X X X X X X X X X X X X X X X X X X no change no change no change no change no change no change no change no change no change no change no change no change no change no change no change no change no change no change no change no change no change no change no change no change ADDR. 9 10 11 12 13 14 15 29 REGISTER Rx Message Counter Rx Buffer Start Address Arbitr. Lost Capture Error Code Capture Error Warning Limit Rx Error Counter Tx Error Counter ACF Mode - - - - - - - BIT SYMBOL RMC RBSA ALC ECC EWLR RXERR TXERR MFORMATB4 AMODEB4 MFORMATB3 AMODEB3 MFORMATB2 AMODEB2 MFORMATB1 AMODEB1 B4F2EN B4F1EN B3F2EN B3F1EN B2F2EN B2F1EN B1F2EN B1F1EN B4F2PRIO B4F1PRIO B3F2PRIO B3F1PRIO B2F2PRIO B2F1PRIO B1F2PRIO B1F1PRIO ACR0 to ACR3 AMR0 to AMR3 ACR0 to ACR3 AMR0 to AMR3 ACR0 to ACR3 AMR0 to AMR3 ACR0 to ACR3 AMR0 to AMR3 RXB TXB - NAME Rx Message Counter Rx Buffer Start Address Arbitration Lost Capture Error Code Capture Error Warning Limit Register Receive Error Counter Transmit Error Counter Message Format Bank4 Accept. Filt. Mode Bank Message Format Bank3 Accept. Filt. Mode Bank3 Message Format Bank2 Accept. Filt. Mode Bank2 Message Format Bank1 Accept. Filt. Mode Bank1 Bank 4 Filter 2 Enable Bank 4 Filter 1 Enable Bank 3 Filter 2 Enable Bank 3 Filter 1 Enable Bank 2 Filter 2 Enable Bank 2 Filter 1 Enable Bank 1 Filter 2 Enable Bank 1 Filter 1 Enable Bank 4 Filter 2 Priority Bank 4 Filter 1 Priority Bank 3 Filter 2 Priority Bank 3 Filter 1 Priority Bank 2 Filter 2 Priority Bank 2 Filter 1 Priority Bank 1 Filter 2 Priority Bank 1 Filter 1 Priority Acceptance Code Register Acceptance Mask Register Acceptance Code Register Acceptance Mask Register Acceptance Code Register Acceptance Mask Register Acceptance Code Register Acceptance Mask Register Receive Buffer Transmit Buffer General Purpose RAM ACFMOD.7 ACFMOD.6 ACFMOD.5 ACFMOD.4 ACFMOD.3 ACFMOD.2 ACFMOD.1 ACFMOD.0 ACFEN.7 ACFEN.6 ACFEN.5 ACFEN.4 ACFEN.3 ACFEN.2 ACFEN.1 ACFEN.0 ACFPRIO.7 ACFPRIO.6 ACFPRIO.5 ACFPRIO.4 ACFPRIO.3 ACFPRIO.2 ACFPRIO.1 ACFPRIO.0 ACR 0 to 3 AMR 0 to 3 - - - - - - - - - - - 30 ACF Enable 31 ACF Priority 32 to 35 36 to 39 40 to 43 44 to 47 48 to 51 52 to 55 56 to 59 60 to 63 96 to 108 112 to 124 125 to 127 Bank 1 X no change X no change X no change X no change X no change X no change X no change X no change X empty (3) X no change X no change X no change X no change X no change X no change X no change X no change X no change X no change X empty (3) X no change X no change Bank 2 ACR 0 to 3 AMR 0 to 3 Bank 3 ACR 0 to 3 AMR 0 to 3 Bank 4 ACR 0 to 3 AMR 0 to 3 Rx Buffer Tx Buffer General Purpose RAM Notes 1. On Bus-Off the Error Warning Interrupt is set, if enabled. 2. If the Reset Mode was entered due to a Bus-off condition, the Receive Error Counter is cleared and the Transmit Error Counter is initialized to 127 to count-down the CAN-defined Bus-off recovery time consisting of 128 occurrences of 11 consecutive recessive bits. 3. Internal read/write pointers of the RXFIFO are reset to their initial values. A subsequent read access to the RXB would show undefined data values (parts of old messages). If a message is transmitted, this message is written in parallel to the Receive Buffer. A Receive Interrupt is generated only, if this transmission was forced by the Self Reception Request. So, even if the Receive Buffer is empty, the last transmitted message may be read from the Receive Buffer until it is overridden by the next received or transmitted message. Upon a Hardware Reset, the RXFIFO pointers are reset to the physical RAM address "0". Setting CR.0 by software or due to the Bus-Off event will reset the RXFIFO pointers to the currently valid FIFO Start Address (RBSA Register) which is different from the RAM address "0" after the first Release Receive Buffer command. 1999 Aug 19 33 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 12.5.2 MODE REGISTER (MOD) P8xC591 The contents of the Mode Register are used to change the behaviour of the CAN Controller. Bits may be set or reset by the CPU that uses the Mode Register as a read / write memory. Reserved Bits are read as "0". Table 13 Mode Register (MOD) CAN Addr. 0 bit interpretation BIT MOD.7 SYMBOL TM NAME Test Mode; Note 1 VALUE 1 (activated) FUNCTION The TX0 pin will reflect the bit, detected on RX pin, with the next positive edge of the system clock. TN0 and TP0 are configured according the setting of OCR. The TXDC output directly reflects RXDC. The RPM bit has no influence within this mode. - RXD inputs are active high (dominant = 1). RXD inputs are active low (dominant = 0). 0 (disabled) MOD.6 MOD.5 RIPM RPM Reserved. Receive Polarity Mode Sleep Mode; Note 2 reserved Self Test Mode; Note 1 - 1 (high active) 0 (low active) MOD.4 SM 1 (high active)) The PeliCAN Block enters Sleep Mode if no CAN interrupt is pending and there is no bus activity. 0 (low active) - 1 (self test) - In this mode a full node test is possible without any other active node on the bus using the Self Reception Request command. The CAN Controller will perform a successful transmission, even if there is no acknowledge received. An acknowledge is required for successful transmission. In this mode the CAN would give no acknowledge to the CAN bus, even if a message is received successfully. No active error flags are driven to the bus. The error counters are stopped at the current value. Normal communication. Setting the Reset Mode bit results in aborting the current transmission/reception of a message and entering the Reset Mode. On the'1'-to-'0' transition of the Reset Mode bit, the CAN Controller returns to the Operating Mode. MOD.3 MOD.2 - STM 0 (normal) MOD.1 LOM Listen Only Mode; Notes 1 and 3 1 (reset) 0 (normal) MOD.0 RM Reset Mode; Note 4 1 (reset) 0 (normal) Notes 1. A write access to the bits MOD.1, MOD.2, MOD.5, MOD.6 and MOD.7 is possible only, if the Reset Mode is entered previously. 2. The PeliCAN Block will enter Sleep Mode, if the Sleep Mode bit is set `1' (sleep), there is no bus activity and no interrupt is pending. Setting of SM with at least one of the previously mentioned exceptions valid will result in a wake-up interrupt. The CAN block will wake up if SM is set LOW (wake-up) or there is bus activity. On wake-up, a Wake-up Interrupt is generated. A sleeping CAN block which wakes up due to bus activity will not be able to receive this message until it detects 11 consecutive recessive bits (Bus-Free sequence). Note that setting of SM is not possible in Reset Mode. After clearing of Reset Mode, setting of SM is possible first, when Bus-Free is detected again. 1999 Aug 19 34 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 3. This mode of operation forces the CAN Controller to be error passive. Message Transmission is not possible. The Listen Only Mode can be used e.g. for software driven bit rate detection and "hot plugging". 4. During a Hardware reset or when the Bus Status bit is set `1' (Bus-Off), the Reset Mode bit is set `1' (present). During an external reset the CPU cannot set the Reset Mode bit `0' (absent). Therefore, after having set the Reset Mode bit `0', the CPU must check this bit to ensure that the external reset pin is not being held HIGH. After the Reset Mode bit is set `0' the CAN Controller will wait for: a) one occurrence of Bus-Free signal (11 recessive bits), if the preceding reset has been caused by Hardware reset or a CPU-initiated reset. b) 128 occurrences of Bus-Free, if the preceding reset has been caused by a CAN Controller initiated Bus-Off, before re-entering the Bus-On mode 12.5.3 COMMAND REGISTER (CMR) The contents of the Command Register are used to change the behaviour of the CAN Controller. Control bits may be set or reset by the CPU which uses the Command Register as a read/write memory. Table 14 Command Register (CMR) CAN Addr. 1, bit interpretation BIT CMR.7 to CMR.5 CMR.4 SYMBOL reserved NAME VALUE FUNCTION SRR Self Reception Request; Notes 1 and 6 Clear Data Overrun; Note 2 Release Receive Buffer; Note 3 Abort Transmission; Notes 4 and 6 Transmission Request; Notes 5 and 6 1 (present) 0 (absent) A message shall be transmitted and received simultaneously. The Data Overrun Status bit is cleared. The Receive Buffer, representing the message memory space in the RXFIFO is released. If not already in progress, a pending Transmission Request is cancelled. A message shall be transmitted. CMR.3 CMR.2 CDO RRB 1 (clear) 0 (no action) 1 (released) 0 (no action) CMR.1 AT 1 (present) 0 (absent) CMR.0 TR 1 (present) 0 (absent) Notes 1. Upon Self Reception Request a message is transmitted and simultaneously received if the acceptance filter is set to the corresponding identifier. A receive and a transmit interrupt will indicate correct self reception. (see also Self Test Mode in Mode Register). 2. This command bit is used to clear the Data Overrun condition signalled by the Data Overrun Status bit. As long as the Data Over run Status bit is set no further Data Overrun Interrupt is generated. 3. After reading the contents of the Receive Buffer, the CPU can release this memory space of the RXFIFO by setting the Release Receive Buffer bit `1'. This may result in another message becoming immediately available within the Receive Buffer. If there is no other message available, the Receive Interrupt bit is reset. The Receive Interrupt is also reset in case there is no "high priority" message available within the FIFO (see acceptance filter description) and the available message bytes are equal to or less to the specified value within the Receive Interrupt Level Register. If the RRB command is given, it will take at least 2 internal clock cycles before a new receive interrupt is generated and Rx Buffer Start Address is updated. 1999 Aug 19 35 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 4. The Abort Transmission bit is used when the CPU requires the suspension of the previously requested transmission, e.g. to transmit a more urgent message before. A transmission already in progress is not stopped. In order to see if the original message had been either transmitted successfully or aborted, the Transmission Complete Status bit should be checked. This should be done after the Transmit Buffer Status bit has been set `1' or a Transmit Interrupt has been generated. 5. If the Transmission Request or the Self Reception Request bit was set `1' in a previous command, it cannot be cancelled by setting the Transmission Request bit `0'. The requested transmission may be cancelled by setting the Abort Transmission bit `1'. 6. Setting the command bits CMR.0 and CMR.1 simultaneously results in transmitting a message once. No re-transmission will be performed in case of an error or arbitration lost (single shot transmission). Setting the command bits CMR.4 and CMR.1 simultaneously results in sending the transmit message once using the self reception feature. No re-transmission will be performed in case of an error or arbitration lost. Setting the command bits CMR.0, CMR.1 and CMR.4 simultaneously results in transmitting a message once as described for CMR.0 and CMR.1. The moment the Transmit Status bit is set within the Status Register, the internal Transmission Request Bit is cleared automatically. Setting CMR.0 and CMR.4 simultaneously will ignore the set CMR.4 bit. 12.5.4 STATUS REGISTER (SR) The content of the Status Register reflects the status of the CAN Controller. The Status Register appears to the CPU as a read only memory. Table 15 Status Register (SR) CAN Addr. 2, bit interpretation BIT SR.7 SR.6 SYMBOL BS ES NAME Bus Status; Note 1 Error Status; Note 2 VALUE 1 (Bus-Off) 0 (Bus-On) 1 (error) 0 (ok) SR.5 SR.4 SR.3 TS RS TCS Transmit Status; Note 3 Receive Status; Note 3 Transmission Complete Status; Note 4 Transmit Buffer Status; Note 5 1 (transmit) 0 (idle) 1 (receive) 0 (idle) 1 (complete) Last requested transmission has been successfully completed. Previously requested transmission is not yet completed The CPU may write a message into the Transmit Buffer. The CPU cannot access the Transmit Buffer. A message is either waiting for transmission or is in transmitting process. A message was lost because there was not enough space for that message in the RXFIFO. No data overrun has occurred since the last Clear Data Overrun command was given One or more complete messages are available in the RXFIFO. No message is available. 36 The CAN Controller is receiving a message. FUNCTION The CAN Controller is not involved in bus activities. The CAN Controller is involved in bus activities At least one of the error counters has reached or exceeded the CPU warning limit (96). Both error counters are below the warning limit. The CAN Controller is transmitting a message. 0 (incomplete) SR.2 TBS 1 (released) 0 (locked) SR.1 DOS Data Overrun Status; Note 6 1 (overrun) 0 (absent) SR.0 RBS Receive Buffer Status; Note 7 1 (full) 0 (empty) 1999 Aug 19 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller Notes to Table 15: P8xC591 1. When the Transmit Error Counter exceeds the limit of 255, the Bus Status bit is set `1' (Bus-Off), the CAN Controller will set the Reset Mode bit `1' (present), an Error Warning and a Bus Error Interrupt is generated, if enabled. The Receive Error Counter is set to `127'. It will stay in this mode until the CPU clears the Reset Request bit. Once this is completed the CAN Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting down the Receive Error Counter. After that the Bus Status bit is cleared (Bus-On), the Error Status bit is set `0' (ok), the Error Counters are reset and an Error Interrupt is generated, if enabled. Reading the RX Error Counter during this time gives information about the status of the Bus-Off recovery. 2. Errors detected during reception or transmission will effect the error counters according to the CAN specification. The Error Status bit is set when at least one of the error counters has reached or exceeded the CPU warning limit of 96. An Error Interrupt is generated, if enabled. 3. If both the Receive Status and the Transmit Status bits are `0' (idle) the CAN-Bus is idle. 4. The Transmission Complete Status bit is set `0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit is set `1'. The Transmission Complete Status bit will remain `0' until a message is transmitted successfully. 5. If the CPU tries to write to the Transmit Buffer when the Transmit Buffer Status bit is `0' (locked), the written byte will not be accepted and will be lost without this being signalled. 6. After reading all messages within the RXFIFO and releasing their memory space with the command Release Receive Buffer this bit is cleared. 7. After reading all messages within the RXFIFO and releasing their memory space with the command Release Receive Buffer this bit is cleared. 1999 Aug 19 37 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 12.5.5 INTERRUPT REGISTER (IR) P8xC591 The Interrupt Register allows the identification of an interrupt source. When one or more bits of this register are set, a CAN interrupt will be indicated to the CPU. After this register is read by the CPU all bits are reset except of the Receive Interrupt bit. The Interrupt Register appears to the CPU as a read only memory. Table 16 Interrupt Register (IR) CAN Addr. 3, bit interpretation BIT IR.7 SYMBOL BEI NAME Bus Error Interrupt VALUE 1 (set) FUNCTION This bit is set when the CAN Controller detects an error on the CAN Bus and the BEIE bit is set within the Interrupt Enable Register. After a bus error interrupt event this interrupt is locked until the Error Code Capture Register is read out once. This bit is set when the CAN Controller has lost arbitration and becomes a receiver and the ALIE bit is set within the Interrupt Enable Register. After an arbitration lost interrupt event this interrupt is locked until the Arbitration Lost Capture Register is read out once. This bit is set whenever the CAN Controller has reached the Error Passive Status (at least one error counter exceeds the CAN protocol defined level of 127) or if the CAN Controller is in Error Passive Status and enters the Error Active Status again and the EPIE bit is set within the Interrupt Enable Register. This bit is set when the CAN Controller is sleeping and bus activity is detected and the WUIE bit is set within the Interrupt Enable Register. This bit is set on a 0-to-1 change of the Data Overrun Status bit, when the Data Overrun Interrupt Enable is set to `1' (enabled). This bit is set on every change (set and clear) of either the Error Status or Bus Status bits if the Error Interrupt Enable is set to `1' (enabled). This bit is set whenever the Transmit Buffer Status changes from `0' to `1' (released) and Transmit Interrupt Enable is set to `1' (enabled). This bit is set whenever the RXFIFO is filled with more bytes than specified in the Rx Interrupt Level register or a message has passed an acceptance filter which is set to "high priority" and the RIE bit is set within the Interrupt Enable Register. 0 (reset) IR.6 ALI Arbitration Lost Interrupt 1 (set) 0 (reset) IR.5 EPI Error Passive Interrupt 1 (set) 0 (reset) IR.4 WUI Wake-Up Interrupt; Note 1 1 (set) 0 (reset) IR.3 DOI Data Overrun Interrupt 1 (set) 0 (reset) IR.2 EI Error Interrupt 1 (set) 0 (reset) IR.1 TI Transmit Interrupt; Note 2 1 (set) 0 (reset) IR.0 RI Receive Interrupt; Note 4 1 (set) 0 (reset) 1999 Aug 19 38 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller Notes to Table 16: P8xC591 1. A Wake-Up Interrupt is also generated, if the CPU tries to set the Sleep bit while the CAN controller is involved in bus activities or a CAN Interrupt is pending. 2. In order to support high priority messages, the Receive Interrupt is forced immediately upon a received message, which has passed successfully an acceptance filter with high priority (see acceptance filter section). As long as only messages are received via low priority acceptance filters, the receive interrupt is not forced until the FIFO is filled with more bytes than programmed in the Rx Interrupt Level Register. The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command "Release Receive Buffer" will clear RI temporarily. If there is another message available within the FIFO after the release command, RI is set again. Otherwise RI keeps cleared. 12.5.6 INTERRUPT ENABLE REGISTER (IER) The register allows to enable different types of interrupt sources which are signalled to the CPU. The Interrupt Enable Register appears to the CPU as a read / write memory. Table 17 Interrupt Enable Register (IER) CAN Addr. 4, bit interpretation BIT IER.7 SYMBOL BEIE NAME Bus Error Interrupt Enable Arbitration Lost Interrupt Enable Error Passive Interrupt Enable VALUE FUNCTION 1 (enabled) If a bus error has been detected, the CAN Controller requests the respective interrupt. 0 (disabled) 1 (enabled) If the CAN Controller has lost arbitration, the respective interrupt is requested. 0 (disabled) 1 (enabled) If the error status of the CAN Controller changes from error active to error passive or vice versa, the respective interrupt is requested. 0 (disabled) 1 (enabled) If the sleeping CAN controller wakes up, the respective interrupt is requested. 0 (disabled) 1 (enabled) If the Data Overrun Status bit is set (see Status Register), the CAN Controller requests the respective interrupt. 0 (disabled) 1 (enabled) If the Error or Bus Status change (see Status Register), the CAN Controller requests the respective interrupt. 0 (disabled) 1 (enabled) When a message has been successfully transmitted or the Transmit Buffer is accessible again, (e.g. after an Abort Transmission command) the CAN Controller requests the respective interrupt. 0 (disabled) 1 (enabled) When the Receive Buffer Status is `full' the CAN Controller requests the respective interrupt. 0 (disabled) IER.6 ALIE IER.5 EPIE IER.4 WUIE Wake-Up Interrupt Enable; Note 1 Data Overrun Interrupt Enable Error Interrupt Enable Transmit Interrupt Enable2 IER.3 DOIE IER.2 EIE IER.1 TIE IER.0 RIE Receive Interrupt Enable; Note 1 Note 1. The Receive Interrupt Enable bit has direct influence to the Receive Interrupt Bit and the interrupt output. If RIE is cleared, the interrupt pin (INT) will become HIGH immediately, if there is no other interrupt pending. 1999 Aug 19 39 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 12.5.7 RX INTERRUPT LEVEL (RIL) P8xC591 The RIL register is used to define the receive interrupt level for the RXFIFO. A receive interrupt is generated if the number of valid CAN message bytes in the RXFIFO exceeds the level specified in this register. Note that receive interrupts are only generated if complete messages have been received. If RIL is set to 00 the PeliCAN functions like the receive interrupt behaviour of the SJA1000. Table 18 Bit interpretation of the Rx Interrupt Level (RIL) CAN ADDR. 5 7 RIL.7 12.5.8 6 RIL.6 5 RIL.5 4 RIL.4 RX INTERRUPT LEVEL (RIL) 3 RIL.3 2 RIL.2 1 RIL.1 0 RIL.0 BUS TIMING REGISTER 0 (BTR0) The contents of the Bus Timing Register 0 defines the values of the Baud Rate Prescaler (BRP) and the Synchronization Jump Width (SJW). This register can be accessed (read/write) if the Reset Mode is active. In Operating Mode, this register is read only. Table 19 Bus Timing Register 0 (BTR0) (CAN address 6) 7 SJW.1 6 SJW.0 5 BRP.5 4 BRP.4 3 BRP.3 2 BRP.2 1 BRP.1 0 BRP.0 12.5.8.1 Baud Rate Prescaler (BRP) The period of the CAN system clock tscl is programmable and determines the individual bit timing. The CAN system clock is calculated using the following equation: x ( 32 x BRP.5 + 16 x BRP.4 + 8 x BRP.3 + 4 x BRP.2 + 2 x BRP.1 + BRP.0 + 1 ) t scl =t CLK t CLK 1 = time period of the Cs system clock = -------------f CLK 12.5.8.2 Synchronization Jump Width (SJW) To compensate for phase shifts between clock oscillators of different bus controllers, any bus controller must resynchronize on any relevant signal edge of the current transmission. The synchronization jump width defines the maximum number of clock cycles a bit period may be shortened or lengthened by one resynchronization: t =t x ( 2 x SJW.1 + SJW.0 + 1 ) SJW scl 1999 Aug 19 40 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 12.5.9 BUS TIMING REGISTER 1 (BTR1) P8xC591 The contents of Bus Timing Register 1 defines the length of the bit period, the location of the sample point and the number of samples to be taken at each bit time. This register can be accessed (read/write) if the Reset Mode is active. In Operating Mode, this register is read only. Table 20 Bus Timing Register 1 (BTR1) (CAN address 7) 7 SAM 6 TSEG2.2 5 TSEG2.1 4 TSEG2.0 3 TSEG1.3 2 TSEG1.2 1 TSEG1.1 0 TSEG1.0. 12.5.9.1 Sampling (SAM) Table 21 Sampling (SAM) BIT SAM 1 (triple) VALUE FUNCTION The bus is sampled three times -> recommended for low/medium speed buses (class A and B) where filtering spikes on the bus-line is beneficial The bus is sampled once -> recommended for high speed buses (SAE class C) 0 (once) 12.5.9.2 Time Segment 1 (TSEG1) and Time Segment 2 (TSEG2) TSEG1 and TSEG2 determine the number of clock cycles per bit period and the location of the sample point: t t TSEG1 =t t scl = 1xt SYNCSEG scl x ( 8 x TSEG1.3 + 4 x TSEG1.2 + 2 x TSEG1.1 + TSEG1.0 + 1 ) =t scl x ( 4 x TSEG2.2 + 2 x TSEG2.1 + TSEG2.0 + 1 ) TSEG2 handbook, full pagewidth C: tscl tCLK baud rate prescaler CAN: tSYNCSEG tTSEG1 nominal bit time tTSEG2 sync. seg. TSEG1 TSEG2 sync. seg. e.g. TSEG1 MHI011 sample point(s) BRP = 000001b TSEG1 = 010b TSEG2 = 010b Fig.12 General structure of a bit period. 1999 Aug 19 41 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 12.5.10 RX MESSAGE COUNTER (RMC) P8xC591 The RMC Register (CAN Address 9) reflects the number of messages available within the RXFIFO. The value is incremented with each receive event and decremented by the Release Receive Buffer command. After any reset event, this register is cleared. Table 22 RX Message Counter (RMC) (CAN address 9) 7 RMC.7 6 RMC.6 5 RMC.5 4 RMC.4 3 RMC.3 2 RMC.2 1 RMC.1 0 RMC.0 12.5.11 RX BUFFER START ADDRESS (RBSA) The RBSA register (CAN Address 10) reflects the currently valid internal RAM address, where the first byte of the received message, which is mapped to the Receive Buffer Window, is stored. With the help of this information it is possible to interpret the internal RAM contents. The internal RAM address area begins at CAN address 32 and may be accessed by the CPU for reading and writing (writing in Reset Mode only). Example: If RBSA is set to 24 (decimal), the current message visible in the Receive Buffer Window (CAN Address 96 -108) is stored within the internal RAM beginning at RAM address 24. Because the RAM is also mapped directly to the CAN address space beginning at CAN address 128 (equal to RAM address 0) this message may also be accessed using CAN address 152 and the following bytes (CAN Address = RBSA + 128--> 24 + 128= 152). Always, the Release Receive Buffer Command is given while there is at least one more message available within the FIFO, RBSA is updated to the beginning of the next message. On Hardware Reset, this pointer is initialised to "00h". Upon a Software Reset (setting of Reset Mode) this pointer keeps its old value, but the FIFO is cleared, what means, that the RAM contents are not changed, but the next received (or transmitted) message will override the currently visible message within the Receive Buffer Window. The RX Buffer Start Address Register appears to the CPU as a read only memory in Operating Mode and as read / write memory in Reset Mode. Table 23 RX Buffer Start Address (RBSA) (CAN address 10) 7 RBSA.7 6 RBSA.6 5 RBSA.5 4 RBSA.4 3 RBSA.3 2 RBSA.2 1 RBSA.1 0 RBSA.0 1999 Aug 19 42 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 12.5.12 ARBITRATION LOST CAPTURE (ALC) P8xC591 This register contains information about the bit position of losing arbitration. The Arbitration Lost Capture Register appears to the CPU as a read only memory. Reserved Bits are read as "0". Table 24 Arbitration Lost Capture (ALC) (CAN address 11) 7 6 5 4 BITNO4 3 BITNO3 2 BITNO2 1 BITNO1 0 BITNO0 Table 25 Description of Arbitration Lost Capture (ALC) Register 1 bits BIT 7 to 5 4 3 2 SYMBOL - BITNO4 BITNO3 BITNO2 NAME - Bit Number 4 Bit Number 3 Bit Number 2 VALUE - Reserved. FUNCTION Binary coded Frame Bit Number where arbitration was lost. 00 -> arbitration lost in first bit of identifier ... 11 -> arbitration lost in SRTR bit (RTR bit for standard frame messages) 12 -> arbitration lost in IDE bit 13 -> arbitration lost in 12th bit of identifier (extended frame only) ... 30 -> arbitration lost in last bit of identifier (extended frame only) 31 -> arbitration lost in RTR bit (extended frame only) 1 0 BITNO1 BITNO0 Bit Number 1 Bit Number 0 On arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. In the same time, the current bit position of the Bit Stream Processor is captured into the Arbitration Lost Capture Register. The content within this register is fixed until the users software has read out its contents once. From now on the capture mechanism is activated again. The corresponding Interrupt Flag located in the Interrupt Register is cleared during the read access to the Interrupt Register. A new Arbitration Lost Interrupt is not possible until the Arbitration Lost Capture Register is read out once. 1999 Aug 19 43 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 start of frame standard and extended frame messages: bit number: ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 ID19 ID18 SRTR IDE 00 01 02 03 04 05 06 07 08 09 10 11 12 extended frame messages: bit number: ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 ID09 ID08 ID07 ID06 ID05 ID04 ID03 ID02 ID01 ID00 RTR 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 arbitration lost ALC = 08 example: TX RX bit number: 00 01 02 03 04 05 06 07 08 MHI013 Fig.13 Arbitration Lost Bit Number Interpretation. 1999 Aug 19 44 handbook, full pagewidth Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 12.5.13 ERROR CODE CAPTURE (ECC) P8xC591 This register contains information about the type and location of errors on the bus. The Error Code Capture Register appears to the CPU as a read only memory. Table 26 Error Code Capture (ECC) (CAN address 12) 7 ERRC1 6 ERRC0 5 DIR 4 SEG4 3 SEG3 2 SEG2 1 SEG1 0 SEG0 Table 27 Description of Error Code Capture (ECC) Register 1 bits BIT SYMBOL 7 6 ERRC1 ERRC0 NAME Error Code 1 Error Code 0 ERRC1 0 0 1 1 1 (RX) 0 (TX) 00011 00010 00110 00100 00111 01111 01110 01100 01101 01001 01011 01010 01000 11000 11001 11011 11010 10010 10001 10110 00011 10111 11100 Start Of Frame ID28 ... ID21 ID20 ... ID18 IDE Bit ID17 ... ID13 ID12 ... ID5 ID4 ... ID0 RTR Bit Reserved Bit 1 Reserved Bit 0 Data Length Code Data Field CRC Sequence CRC Delimiter Acknowledge Slot Acknowledge Delimiter End Of Frame Intermission Active Error Flag Passive Error Flag Tolerate Dom. Bits Error Delimiter Overload Flag VALUE ERRC0 0 1 0 1 Bit Error Form Error Stuff Error Other Error Error occurred during reception Error occurred during transmission FUNCTION 5 4 3 2 1 0 DIR SEG4 SEG3 SEG2 SEG1 SEG0 Direction Segment 4 Segment 3 Segment 2 Segment 1 Segment 0 Reflects the current Frame Segment to determine between different error events: Always if a bus error occurs, the corresponding bus error interrupt is forced, if enabled. In the same time, the current position of the Bit Stream Processor is captured into the Error Code Capture Register. The content within this register is fixed until the users software has read out its content once. From now on the capture mechanism is activated again. The corresponding Interrupt Flag located in the Interrupt Register is cleared during the read access to the Interrupt Register. A new Bus Error Interrupt is not possible until the Capture Register is read out once. 1999 Aug 19 45 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 12.5.14 ERROR WARNING LIMIT REGISTER (EWLR) P8xC591 The Error Warning Limit could be defined within this register. The default value (after hardware reset) is 96d. In Reset Mode this register appears to the CPU as a read / write memory. Table 28 Error Warning Limit Register (EWLR) (CAN address 13) 7 EWL.7 6 EWL.6 5 EWL.5 4 EWL.4 3 EWL.3 2 EWL.2 1 EWL.1 0 EWL.0 Note that a content change of the EWL-Register is possible only, if the Reset Mode was entered previously. An Error Status change (Status Register) and an Error Warning Interrupt forced by the new register content will not occur, until the Reset Mode is cancelled again. 12.5.15 RX ERROR COUNTER REGISTER (RXERR) The RX Error Counter Register reflects the current value of the Receive Error Counter. After hardware reset this register is initialised to "0". In Operating Mode this register appears to the CPU as a read only memory. A write access to this register is possible only in Reset Mode. If a Bus Off event occurs, the RX Error counter is initialised to "0". As long as Bus Off is valid, writing to this register has no effect. Table 29 RX Error Counter Register (RXERR) (CAN address 14) 7 RXERR.7 6 RXERR.6 5 RXERR.5 4 RXERR.4 3 RXERR.3 2 RXERR.2 1 RXERR.1 0 RXERR.0 Note that a CPU-forced content change of the RX Error Counter is possible only, if the Reset Mode was entered previously. An Error Status change (Status Register), an Error Warning or an Error Passive Interrupt forced by the new register content will not occur, until the Reset Mode is cancelled again. 1999 Aug 19 46 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 12.5.16 TX ERROR COUNTER REGISTER (TXERR) The TX Error Counter Register reflects the current value of the Transmit Error Counter. In Operating Mode this register appears to the CPU as a read only memory. A write access to this register is possible only in Reset Mode. After hardware reset this register is initialised to "0". If a bus-off event occurs, the TX Error Counter is initialised to 127 to count the minimum protocol-defined time (128 occurrences of the Bus-Free signal). Reading the TX Error Counter during this time gives information about the status of the Bus-Off recovery. If Bus Off is active, a write access to TXERR in the range of 0 to 254 clears the Bus Off Flag and the controller will wait for one occurrence of 11 consecutive recessive bits (bus free) after clearing of Reset Mode. Writing 255 to TXERR allows to initiate a CPU-driven Bus Off event. Note, that a CPU-forced content change of the P8xC591 TX Error Counter is possible only, if the Reset Mode was entered previously. An Error or Bus Status change (Status Register), an Error Warning or an Error Passive Interrupt forced by the new register content will not occur, until the Reset Mode is cancelled again. After leaving the Reset Mode, the new TX Counter content is interpreted and the Bus Off event is performed in the same way, as if it was forced by a bus error event. That means, that the Reset Mode is entered again, the TX Error Counter is initialised to 127, the RX Counter is cleared and all concerned Status and Interrupt Register Bits are set. Clearing of Reset Mode now will perform the protocol defined Bus Off recovery sequence (waiting for 128 occurrences of the Bus-Free signal). If the Reset Mode is entered again before the end of Bus Off recovery (TXERR > 0), Bus Off keeps active and TXERR is frozen. Table 30 TX Error Counter Register (TXERR) (CAN address 15) 7 TXERR.7 6 TXERR.6 5 TXERR.5 4 TXERR.4 3 TXERR.3 2 TXERR.2 1 TXERR.1 0 TXERR.0 12.5.17 ACCEPTANCE FILTER With the help of the Acceptance Filter the CAN Controller is able to allow passing of received messages to the RXFIFO only when the identifier bits and the Frame Type of the received message are equal to the predefined ones within the Acceptance Filter Registers. If at least one filter matches, the message is copied to the receive FIFO. The Acceptance Filter is defined by the Acceptance Code Registers (ACRn) and the Acceptance Mask Registers (AMRn). Within the Acceptance Code Registers the bit patterns of messages to be received are defined. The corresponding Acceptance Mask Registers allow defining certain bit positions to be "don`t care". The PeliCAN is designed to support four of so called Acceptance Filter Banks. Each bank has the functionality known from the SJA1000 with the extension, that a filter change is possible "on the fly". Additionally the used Frame Format of each filter bank is programmable now. 1999 Aug 19 47 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 handbook, full pagewidth ACCEPTANCE FILTER MODE REGISTER AMODEB4 MFORMATB3 standard/ extended AMODEB3 MFORMATB2 standard/ extended AMODEB2 MFORMATB1 standard/ extended AMODEB1 MFORMATB4 standard/ extended dual/single dual/single dual/single dual/single ACCEPTANCE FILTER BANK 4 ACR 0 ACR 1 ACR 2 ACR 3 AMR 0 AMR 1 AMR 2 AMR 3 ACCEPTANCE FILTER BANK 3 ACR 0 ACR 1 ACR 2 ACR 3 AMR 0 AMR 1 AMR 2 AMR 3 ACCEPTANCE FILTER BANK 2 ACR 0 ACR 1 ACR 2 ACR 3 AMR 0 AMR 1 AMR 2 AMR 3 ACCEPTANCE FILTER BANK 1 ACR 0 ACR 1 ACR 2 ACR 3 AMR 0 AMR 1 AMR 2 AMR 3 filter 2 enable/ disable B4F2EN filter 1 enable/ disable B4F1EN filter 2 enable/ disable B3F2EN filter 1 enable/ disable B3F1EN filter 2 enable/ disable B2F2EN filter 1 enable/ disable B2F1EN filter 2 enable/ disable B1F2EN filter 1 enable/ disable B1F1EN ACCEPTANCE FILTER ENABLE REGISTER filter 2 priority low/high B4F2PRIO filter 1 priority low/high B4F1PRIO filter 2 priority low/high B3F2PRIO filter 1 priority low/high B3F1PRIO filter 2 priority low/high B2F2PRIO filter 1 priority low/high B2F1PRIO filter 2 priority low/high B1F2PRIO filter 1 priority low/high B1F1PRIO ACCEPTANCE FILTER PRIORITY REGISTER MHI014 Fig.14 Acceptance Filter Tables. 1999 Aug 19 48 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 12.5.17.1 Acceptance Filter Mode Register P8xC591 The current operating mode is defined within the Acceptance Filter Mode Register located at CAN Address 29. A write access to this register is possible only within Reset Mode (Mode Register). Note, that some bits are implemented only in case of the corresponding acceptance filter bank is implemented. Not implemented bits are read as "0". Table 31 Acceptance Filter Mode Register (ACF Mode) (CAN address 29) 7 MFORMATB4 6 AMODEB4 5 MFORMATB3 4 AMODEB3 3 MFORMATB2 2 AMODEB2 1 MFORMATB1 0 AMODEB1 Table 32 Acceptance Filter Mode Register (ACF Mode) 1 bits BIT ACFMOD.7 SYMBOL NAME VALUE 1 (EFF) 0 (SFF) ACFMOD.6 AMODEB4 Acceptance Filter Mode Bank 4 FUNCTION Acceptance Filter Bank 4 is used for Extended Frame Messages only, Standard Frame Messages are ignored Acceptance Filter Bank 4 is used for Standard Frame Messages only, Extended Frame Messages are ignored MFORMATB4 Acceptance Filter Format Bank 4 1 (single) The Single Acceptance Filter option is enabled for filter bank 4, -> one long filter is active 0 (dual) The Dual Acceptance Filter option is enabled for filter bank 4, -> two short filters are active Acceptance Filter Bank 3 is used for Extended Frame Messages only, Standard Frame Messages are ignored Acceptance Filter Bank 3 is used for Standard Frame Messages only, Extended Frame Messages are ignored ACFMOD.5 MFORMATB3 Acceptance Filter Format Bank 3 1 (EFF) 0 (SFF) ACFMOD..4 AMODEB3 Acceptance Filter Mode Bank 3 1 (single) The Single Acceptance Filter option is enabled for filter bank 3, -> one long filter is active 0 (dual) The Dual Acceptance Filter option is enabled for filter bank 3, -> two short filters are active Acceptance Filter Bank 2 is used for Extended Frame Messages only, Standard Frame Messages are ignored. Acceptance Filter Bank 2 is used for Standard Frame Messages only, Extended Frame Messages are ignored. ACFMOD.3 MFORMATB2 Acceptance Filter Format Bank 2 1 (EFF) 0 (SFF) ACFMOD.2 AMODEB2 Acceptance Filter Mode Bank 2 1 (single) The Single Acceptance Filter option is enabled for filter bank 2, -> one long filter is active 0 (dual) The Dual Acceptance Filter option is enabled for filter bank 2, -> two short filters are active Acceptance Filter Bank 1 is used for Extended Frame Messages only, Standard Frame Messages are ignored Acceptance Filter Bank 1 is used for Standard Frame Messages only, Extended Frame Messages are ignored ACFMOD.1 MFORMATB1 Acceptance Filter Format Bank 1 1 (EFF) 0 (SFF) ACFMOD.0 AMODEB1 Acceptance Filter Mode Bank 1 1 (single) The Single Acceptance Filter option is enabled for filter bank 1, -> one long filter is active 0 (dual) The Dual Acceptance Filter option is enabled for filter bank 1, -> two short filters are active 1999 Aug 19 49 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 12.5.17.2 Acceptance Filter Enable Register P8xC591 Each defined Acceptance Filter is enabled or disabled by a certain bit located within the Acceptance Filter Enable Register. This allows to change the Acceptance Filter Contents "on the fly" during normal operation if the corresponding filter is disabled previously. A disabled Acceptance Filter does not allow passing of messages to the receive buffer. If all Acceptance Filters are disabled (default after hardware reset) no messages will pass to the receive buffer at all. The Acceptance Code and Mask registers are writable only, if the related Acceptance Filter is disabled or the CAN Block is in Reset Mode. Note, that some bits are implemented only in case of the corresponding acceptance filter bank is implemented. Not implemented bits are read as "0". Table 33 Acceptance Filter Enable Register (ACF Enable) (CAN address 30) 7 B4F2EN 6 B4F1EN 5 B3F2EN 4 B3F1EN 3 B2F2EN 2 B2F1EN 1 B1F2EN 0 B1F1EN Table 34 Acceptance Filter Enable Register (ACF Enable) BIT ACFEN.7 SYMBOL B4F2EN NAME Bank 4 Filter 2 Enable VALUE FUNCTION 1 (enabled) Filter 2 of Bank 4 is enabled, no write access to corresponding Mask and Code Registers is possible 0 (disabled) Filter 2 of Bank 4 is enabled, changing of corresponding Mask and Code Registers is possible. 1 (enabled) Filter 1 of Bank 4 is enabled, no write access to corresponding Mask and Code Registers is possible 0 (disabled) Filter 1 of Bank 4 is enabled, changing of corresponding Mask and Code Registers is possible. 1 (enabled) Filter 2 of Bank 3 is enabled, no write access to corresponding Mask and Code Registers is possible 0 (disabled) Filter 2 of Bank 3 is enabled, changing of corresponding Mask and Code Registers is possible. 1 (enabled) Filter 1 of Bank 3 is enabled, no write access to corresponding Mask and Code Registers is possible 0 (disabled) Filter 1 of Bank 3 is enabled, changing of corresponding Mask and Code Registers is possible. 1 (enabled) Filter 2 of Bank 2 is enabled, no write access to corresponding Mask and Code Registers is possible 0 (disabled) Filter 2 of Bank 2 is enabled, changing of corresponding Mask and Code Registers is possible. 1 (enabled) Filter 1 of Bank 2 is enabled, no write access to corresponding Mask and Code Registers is possible 0 (disabled) Filter 1 of Bank 2 is enabled, changing of corresponding Mask and Code Registers is possible. 1 (enabled) Filter 2 of Bank 1 is enabled, no write access to corresponding Mask and Code Registers is possible 0 (disabled) Filter 2 of Bank 1 is enabled, changing of corresponding Mask and Code Registers is possible. 1 (enabled) Filter 1 of Bank 1 is enabled, no write access to corresponding Mask and Code Registers is possible 0 (disabled) Filter 1 of Bank 1 is enabled, changing of corresponding Mask and Code Registers is possible. ACFEN.6 B4F1EN Bank 4 Filter 1 Enable ACFEN.5 B3F2EN Bank 3 Filter 2 Enable ACFEN.4 B3F1EN Bank 3 Filter 1 Enable ACFEN.3 B2F2EN Bank 2 Filter 2 Enable ACFEN.2 B2F1EN Bank 2 Filter 1 Enable ACFEN.1 B1F2EN Bank 1 Filter 2 Enable ACFEN.0 B1F1EN Bank 1 Filter 1 Enable Note, if the Single Filter Mode is selected for an Acceptance Filter Bank, this single filter is related to the corresponding Filter 1 Enable Bit. The Filter 2 Enable Bits have no influence within Single Filter Mode. 1999 Aug 19 50 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 12.5.17.3 Acceptance Filter Priority Register P8xC591 For each available Acceptance Filter it could be defined, whether a receive interrupt is forced immediately if a message passes a certain Acceptance Filter or whether the programmed Receive Interrupt Level should be used for interruption. This allows to use certain Acceptance Filters for alarm message recognition interrupting the host CPU immediately. Note, that some bits are implemented only in case of the corresponding acceptance filter bank is implemented. Not implemented bits are read as "0". Table 35 Acceptance Filter Priority Register (ACF Priority) (CAN address 31) 7 B4F2PRIO 6 B4F1PRIO 5 B3F2PRIO 4 B3F1PRIO 3 B2F2PRIO 2 B2F1PRIO 1 B1F2PRIO 0 B1F1PRIO Table 36 Acceptance Filter Priority Register (ACF Priority) BIT SYMBOL NAME VALUE 1 (high) 0 (low) ACFPRIO.6 B4F1PRIO Bank 4 Filter 1 Priority 1 (high) 0 (low) ACFPRIO.5 B3F2PRIO Bank 3 Filter 2 Priority 1 (high) 0 (low) ACFPRIO.4 B3F1PRIO Bank 3 Filter 1 Priority 1 (high) 0 (low) ACFPRIO.3 B2F2PRIO Bank 2Filter 2 Priority 1 (high) 0 (low) ACFPRIO.2 B2F1PRIO Bank 2 Filter 1 Priority 1 (high) 0 (low) ACFPRIO.1 B1F2PRIO Bank 1 Filter 2 Priority 1 (high) 0 (low) ACFPRIO.0 B1F1PRIO Bank 1 Filter 1 Priority 1 (high) 0 (low) FUNCTION A receive interrupt is generated immediately, if a message passes Filter 2 within Acceptance Filter Bank 4 A receive interrupt is generated, if the FIFO level exceeds the Receive Interrupt Level Register. A receive interrupt is generated immediately, if a message passes Filter 1 within Acceptance Filter Bank 4 A receive interrupt is generated, if the FIFO level exceeds the Receive Interrupt Level Register. A receive interrupt is generated immediately, if a message passes Filter 2 within Acceptance Filter Bank 3 A receive interrupt is generated, if the FIFO level exceeds the Receive Interrupt Level Register. A receive interrupt is generated immediately, if a message passes Filter 1 within Acceptance Filter Bank 3 A receive interrupt is generated, if the FIFO level exceeds the Receive Interrupt Level Register. A receive interrupt is generated immediately, if a message passes Filter 2 within Acceptance Filter Bank 2 A receive interrupt is generated, if the FIFO level exceeds the Receive Interrupt Level Register. A receive interrupt is generated immediately, if a message passes Filter 1 within Acceptance Filter Bank 2 A receive interrupt is generated, if the FIFO level exceeds the Receive Interrupt Level Register. A receive interrupt is generated immediately, if a message passes Filter 2 within Acceptance Filter Bank 1 A receive interrupt is generated, if the FIFO level exceeds the Receive Interrupt Level Register. A receive interrupt is generated immediately, if a message passes Filter 1 within Acceptance Filter Bank 1 A receive interrupt is generated, if the FIFO level exceeds the Receive Interrupt Level Register. ACFPRIO.7 B4F2PRIO Bank 4 Filter 2 Priority 1999 Aug 19 51 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 12.5.17.4 Single Filter Configuration In this filter configuration one long filter (4-byte) could be defined. The bit correspondences between the filter bytes and the Message bytes depends on the programmed Frame Format (see ACF Mode Register). Single Filter Standard Frame: If the Standard Frame Format is selected, the complete Identifier including the RTR bit and the first two data bytes are used for acceptance filtering. Messages may also be P8xC591 accepted if there are no data bytes existing due to a set RTR bit or if there is no or only one data byte because of the corresponding data length code. For a successful reception of a message, all single bit comparisons have to signal acceptance. Note that the 4 least significant bits of AMR1 and ACR1 are not used. In order to keep compatible with future products these bits should be programmed to be "don`t care" by setting AMR1.3, AMR1.2, AMR1.1 and AMR1.0 to "1". MSB handbook, full pagewidth Addr.: 16 7 6 5 4 3 2 1 LSB MSB ACR0 0 Addr.: 17 7 6 5 4 3 2 1 LSB MSB ACR1 0 Addr.: 18 7 6 5 4 3 2 1 LSB MSB ACR2 0 Addr.: 19 7 6 5 4 3 2 1 LSB ACR3 0 MSB Addr.: 20 7 6 5 4 3 2 1 LSB MSB AMR0 0 Addr.: 21 7 6 5 4 3 unused LSB MSB AMR1 2 1 0 Addr.: 22 7 6 5 4 3 2 1 LSB MSB AMR2 0 Addr.: 23 7 6 5 4 3 2 1 LSB AMR3 0 unused DB1.7 DB1.6 DB1.5 DB1.4 DB1.3 DB1.2 DB1.1 DB1.0 DB2.7 DB2.6 DB2.5 DB2.4 DB2.3 DB2.2 DB2.1 DB2.0 ID.28 ID.27 ID.26 ID.25 ID.24 ID.23 ID.22 ID.21 ID.20 ID.19 ID.18 RTR MHI015 Message Bit Acceptance Code Bit Acceptance Mask Bit = DBx.y = Data Byte x, Bit y 1 [0] & 1 0 accepted not accepted [6] [7] Fig.15 Single Filter Configuration, receiving Standard Frame Messages. 1999 Aug 19 52 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller Single Filter Extended Frame: If the Extended Frame Format is selected, the complete Identifier including the RTR bit is used for acceptance filtering. For a successful reception of a message, all single bit comparisons have to signal acceptance. Note that the 2 P8xC591 least significant bits of AMR3 and ACR3 are not used. In order to keep compatible with future products these bits should be programmed to be "don`t care" by setting AMR3.1 and AMR3.0 to "1". MSB handbook, full pagewidth Addr.: 16 7 6 5 4 3 2 1 LSB MSB ACR0 0 Addr.: 17 7 6 5 4 3 2 1 LSB MSB ACR1 0 Addr.: 18 7 6 5 4 3 2 1 LSB MSB ACR2 0 Addr.: 19 7 6 5 4 3 2 1 LSB ACR3 0 MSB Addr.: 20 7 6 5 4 3 2 1 LSB MSB AMR0 0 Addr.: 21 7 6 5 4 3 2 1 LSB MSB AMR1 0 Addr.: 22 7 6 5 4 3 2 1 LSB MSB AMR2 0 Addr.: 23 7 6 5 4 3 2 unused LSB AMR3 1 0 unused ID.28 ID.27 ID.26 ID.25 ID.24 ID.23 ID.22 ID.21 ID.20 ID.19 ID.18 ID.17 ID.16 ID.15 ID.14 ID.13 ID.12 ID.11 ID.10 RTR MHI016 ID.5 ID.4 ID.3 ID.2 ID.1 ID.9 ID.8 ID.7 Message Bit Acceptance Code Bit Acceptance Mask Bit = 1 [0] & 1 0 accepted not accepted [6] [7] Fig.16 Single Filter Configuration, receiving Extended Frame Messages. 1999 Aug 19 53 ID.6 ID.0 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 12.5.17.5 Dual Filter Configuration In this filter configuration two short filters could be defined. A received message is compared with both filters to decide, whether this message should be copied into the Receive Buffer or not. If at least one of the filters signals an acceptance, the received message becomes valid. The bit correspondences between the filter bytes and the message bytes depends on the currently received Frame Format. Dual Filter Standard Frame: P8xC591 If the Standard Frame Format is selected, the two defined filters are different. The first filter compares the complete Standard Identifier including the RTR bit and the first Data Byte of the message. The second filter just compares the complete Standard Identifier including the RTR bit. handbook, full pagewidth MSB Addr.: 16 7 Filter 1 MSB Addr.: 20 7 6 5 4 3 2 1 6 5 4 3 2 1 LSB MSB ACR0 0 Addr.: 17 7 6 5 4 3 2 1 LSB ACR1 0 3 2 1 LSB ACR3 0 LSB MSB AMR0 0 Addr.: 21 7 6 5 4 3 2 1 LSB AMR1 0 3 2 1 LSB AMR3 0 DB1.7 DB1.6 DB1.5 DB1.4 DB1.3 DB1.2 DB1.1 Message Addr.: 22 6 MSB Filter 2 Addr.: 18 7 6 5 4 3 MSB 7 5 4 3 AMR2 2 1 Addr.: 23 5 4 AMR3 76 0 LSB MSB ACR2 2 1 0 Addr.: 19 7 6 5 4 ACR3 LSB MSB [7] & Filter 1 . . . Acceptance Mask Bit Acceptance Code Bit Message Bit = Acceptance Code Bit Acceptance Mask Bit 1 = 1 [6] ... ... ... [0] 1 1 0 accepted not accepted [0] . . . ... ... ... [6] [7] & Filter 2 MHI017 Fig.17 Dual Filter Configuration, receiving Standard Frame Messages. 1999 Aug 19 54 DB1.0 ID.28 ID.27 ID.26 ID.25 ID.24 ID.23 ID.22 ID.21 ID.20 ID.19 ID.18 RTR Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller For a successful reception of a message, all single bit comparisons of at least one complete filter have to signal acceptance. In case of a set RTR bit or a data length code of "0" no data byte is existing. Nevertheless, a message may pass Filter 1, if the first part up to the RTR bit signals acceptance. If no data byte filtering is required for Filter 1, the four least significant bits of AMR1 and AMR3 have to be set "1" (don`t care). Then both filters are working identically using the standard identifier range including the RTR bit. Dual Filter Extended Frame: P8xC591 If the Extended Frame Format is selected, the two defined filters are looking identically. Both filters are comparing the first two bytes of the Extended Identifier range only. For a successful reception of a message, all single bit comparisons of at least one complete filter have to signal acceptance. handbook, full pagewidth MSB Addr.: 16 7 Filter 1 MSB Addr.: 20 7 6 5 4 3 2 1 6 5 4 3 2 1 LSB MSB ACR0 0 Addr.: 17 7 6 5 4 3 2 1 LSB ACR1 0 LSB MSB AMR0 0 Addr.: 21 7 6 5 4 3 2 1 LSB AMR1 0 ID.28 ID.27 ID.26 ID.25 ID.24 ID.23 ID.22 ID.21 ID.20 ID.19 ID.18 ID.17 ID.16 ID.15 2 ID.14 1 1 Message Addr.: 22 76 MSB Filter 2 Addr.: 18 7 6 5 4 3 MSB 5 4 3 AMR2 2 1 Addr.: 23 5 4 3 AMR3 0 LSB 0 76 LSB MSB ACR2 2 1 0 Addr.: 19 7 6 5 4 3 ACR3 2 0 LSB LSB MSB Filter 1 [7] & . . . Acceptance Mask Bit Acceptance Code Bit Message Bit = Acceptance Code Bit Acceptance Mask Bit 1 = 1 [6] ... ... ... [0] 1 1 0 accepted not accepted [0] . . . ... ... ... [6] [7] & Filter 2 ID.13 MHI018 Fig.18 Dual Filter Configuration, receiving Extended Frame Messages. 1999 Aug 19 55 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 12.5.18 TRANSMIT BUFFER The global layout of the Transmit Buffer is shown in Fig.19. One has to distinguish between the Standard Frame Format (SFF) and the Extended Frame Format (EFF) configuration. The transmit buffer allows the definition of one transmit message with up to eight data bytes. P8xC591 12.5.18.1 Transmit Buffer Layout It is subdivided into Descriptor and Data Field where the first byte of the Descriptor Field is the Frame Information Byte (Frame Info). It describes the Frame Format (SFF or EFF), Remote or Data Frame and the Data Length. Two identifier bytes for SFF and four bytes for EFF messages follow. The Data Field contains up to eight data bytes. The Transmit Buffer has a length of 13 bytes and is located in the CAN address range from 112 to 124. handbook, full pagewidth Standard Frame Format (SFF) 112 113 114 115 116 117 118 119 120 121 122 123 124 TX Frame information TX Identifier 1 TX Identifier 2 TX Data byte 1 TX Data byte 2 TX Data byte 3 TX Data byte 4 TX Data byte 5 TX Data byte 6 TX Data byte 7 TX Data byte 8 unused unused CAN Address Extended Frame Format (EFF) 112 113 114 115 116 117 118 119 120 121 122 123 124 TX Frame information TX Identifier 1 TX Identifier 2 TX Identifier 3 TX Identifier 4 TX Data byte 1 TX Data byte 2 TX Data byte 3 TX Data byte 4 TX Data byte 5 TX Data byte 6 TX Data byte 7 TX Data byte 8 MHI023 CAN Address Fig.19 Transmit Buffer Layout for Standard and Extended Frame Format configurations. 1999 Aug 19 56 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 12.5.18.2 Descriptor Field of the Transmit Buffer P8xC591 Standard Frame Format (SFF) Addr. 112 7 FF 6 RTR TX Frame Information 5 (0) 4 (0) 3 2 1 0 Addr. 112 7 FF Extended Frame Format (EFF) TX Frame Information 5 (0) 4 (0) 3 2 1 0 6 RTR DLC.3 DLC.2 DLC.1 DLC.0 DLC.3 DLC.2 DLC.1 DLC.0 Addr 113 7 ID.28 6 ID.27 TX Identifier 1 5 ID.26 4 ID.25 3 ID.24 2 ID.23 1 ID.22 0 ID.21 Addr. 113 7 ID.28 6 ID.27 TX Identifier 1 5 ID.26 4 ID.25 3 ID.24 2 ID.23 1 ID.22 0 ID.21 Addr. 114 7 ID.20 6 ID.19 TX Identifier 2 5 4 3 (0) 2 (0) 1 (0) 0 (0) Addr. 114 7 ID.20 6 ID.19 TX Identifier 2 5 ID.18 4 ID.17 3 ID.16 2 ID.15 1 ID.14 0 ID.13 ID.18 (RTR) Meaning of the Transmit Buffer Bits: ID.x FF RTR DLC.x X 0 Identifier bit x Frame Format Remote Transmission Request Data Length Code bit x don't care don't care, but recommended to be compatible to Receive Buffer Addr. 115 7 ID.12 6 ID.11 TX Identifier 3 5 ID.10 4 ID.9 3 ID.8 2 ID.7 1 ID.6 0 ID.5 Addr. 116 7 ID.4 6 ID.3 TX Identifier 4 5 ID.2 4 ID.1 3 ID.0 2 (RTR) 1 (0) 0 (0) Fig.20 Bit Layout Transmit Buffer. This configuration is chosen to be compatible with the Receive Buffer Layout (see Section 12.5.19.1). The values marked with "( )" in the Transmit Buffer should be set to the values expected in the Receive Buffer for an easy comparison, only when using the Self Reception facility, otherwise they are don't care. Table 37 Frame Format (FF) and Remote Transmission Request (RTR) bits BIT FF RTR 1 (EFF) 0 (SFF) 1 (remote) 0 (data) VALUE FUNCTION Extended Frame Format will be transmitted by the CAN Controller Standard Frame Format will be transmitted by the CAN Controller Remote Frame will be transmitted by the CAN Controller Data Frame will be transmitted by the CAN Controller 1999 Aug 19 57 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 12.5.18.3 Data Length Code (DLC) The number of bytes in the Data Field of a message is coded by the Data Length Code. At the start of a Remote Frame transmission the Data Length Code is not considered due to the RTR bit being `1' (remote). This forces the number of transmitted/received data bytes to be 0. Nevertheless, the Data Length Code must be specified correctly to avoid bus errors, if two CAN Controllers start a Remote Frame transmission with the same identifier simultaneously. The range of the Data Byte Count is 0 to 8 bytes and is coded as follows: P8xC591 DataByteCount = 8 x DLC.3 + 4 x DLC.2 + 2 x DLC.1 + DLC.0 For reasons of compatibility no Data Length Code > 8 should be used. If a value greater than 8 is selected, 8 bytes are transmitted in the data frame with the Data Length Code specified in DLC. 12.5.18.4 Identifier (ID) In Standard Frame Format (SFF) the Identifier consists of 11 bits (ID.28 to ID.18) and in Extended Frame Format (EFF) messages the identifier consists of 29 bits (ID.28 to ID.0). ID.28 is the most significant bit, which is transmitted first on the bus during the arbitration process. The Identifier acts as the message's name, used in a receiver for acceptance filtering, and also determines the bus access priority during the arbitration process. The lower the binary value of the Identifier the higher the priority. This is due to the larger number of leading dominant bits during arbitration. 12.5.18.5 Data Field The number of transferred data bytes is defined by the Data Length Code. The first bit transmitted is the most significant bit of data byte 1 at address 115 (SFF) or address 117 (EFF). 1999 Aug 19 58 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 12.5.19 RECEIVE BUFFER P8xC591 The global layout of the Receive Buffer is very similar to the Transmit Buffer described in the previous chapter. The Receive Buffer is the accessible part of the RXFIFO and is located in the range between CAN Address 96 and 108. Each message is subdivided into a Descriptor and a Data Field. handbook, full pagewidth message 3 receive FIFO 108 107 message 2 106 105 104 103 102 101 100 incoming messages receive buffer window message 1 99 98 97 96 MHI019 Message 1 is now available in the Receive Buffer Note that message 2 should not be read until it has been shifted to address 96 by a Release Receive Buffer Command because this message may be in process now and due to this not fixed. Fig.21 Example of the message storage within the RXFIFO. 1999 Aug 19 59 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 12.5.19.1 Descriptor File of the Receive Buffer P8xC591 Identifier, Frame Format, Remote Transmission Request bit and Data Length Code have the same meaning as described in the Transmit Buffer. Standard Frame Format (SFF) Addr. 96 7 FF 6 RTR RX Frame Information 5 0 4 0 3 2 1 0 DLC.3 DLC.2 DLC.1 DLC.0 Addr. 96 7 FF Extended Frame Format (EFF) RX Frame Information 6 RTR 5 0 4 0 3 2 1 0 DLC.3 DLC.2 DLC.1 DLC.0 Addr. 97 7 ID.28 6 ID.27 RX Identifier 1 5 ID.26 4 ID.25 3 ID.24 2 ID.23 1 ID.22 0 ID.21 Addr. 97 7 ID.28 6 ID.27 RX Identifier 1 5 ID.26 4 ID.25 3 ID.24 2 ID.23 1 ID.22 0 ID.21 Addr. 98 7 ID.20 6 ID.19 RX Identifier 2 5 ID.18 4 RTR 3 0 2 0 1 0 0 0 Addr. 98 7 ID.20 6 ID.19 RX Identifier 2 5 ID.18 4 ID.17 3 ID.16 2 ID.15 1 ID.14 0 ID.13 Meaning of the Receive Buffer Bits: ID.x IDX.x FF RTR DLC.x Identifier bit x Index bit x Frame Format Remote Transmission Request Data Length Code bit x Addr. 99 7 ID.12 6 ID.11 RX Identifier 3 5 ID.10 4 ID.9 3 ID.8 2 ID.7 1 ID.6 0 ID.5 Addr. 100 7 ID.4 6 ID.3 RX Identifier 4 5 ID.2 4 ID.1 3 ID.0 2 RTR 1 0 0 0 Fig.22 Bit Layout Receive Buffer. Note: The received Data Length Code located in the Frame Information Byte represents the real sent Data Length Code, which may be greater than 8 (depends on transmitting CAN node). Nevertheless, the maximum number of received data bytes is 8. This should be taken into account by reading a message from the Receive Buffer. It depends on the data length how many CAN messages can fit in the RXFIFO at one time. If there is not enough space for a new message within the RXFIFO, the CAN Controller generates a Data Overrun condition the moment this message becomes valid and the acceptance 1999 Aug 19 60 test was positive. A message that is partly written into the RXFIFO, when the Data Overrun situation occurs, is deleted. This situation is signalled to the CPU via the Status Register and the Data Overrun Interrupt, if enabled. It depends on the data length how many CAN messages can fit in the RXFIFO at one time. If there is not enough space for a new message within the RXFIFO, the CAN Controller generates a Data Overrun condition the moment this message becomes valid and the acceptance test was positive. A message that is partly written into the RXFIFO, when the Data Overrun situation occurs, is deleted. This situation is signalled to the CPU via the Status Register and the Data Overrun Interrupt, if enabled. Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 13 SERIAL I/O The P8xC591 is equipped with three independent serial ports: CAN, SIO0 and SIO1. SIO0 is a Standard Serial Interface UART with enhanced functionality. In following there will be one Section describing the Standard UART functionality and an extra Section for Enhanced UART. SIO1 accommodates the I2C bus. 14 SIO0 STANDARD SERIAL INTERFACE UART The serial port is full duplex, meaning it can transmit and receive simultaneously. It is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the register. (However, if the first byte still hasn't been read by the time reception of the second byte is complete, one of the bytes will be lost.) The serial port receive and transmit registers are both accessed at Special Function Register transmit registers are both accessed at Special Function Register S0BUF. Writing to S0BUF loads the transmit register, and reading S0BUF accesses a physically separate receive register. The serial port can operate in 4 modes (one synchronous mode, three asynchronous modes). The baud rate clock for the serial port is derived from the oscillator frequency (mode 0, 2) or generated either by timer 1 or by dedicated baud rate generator (mode 1, 3). Mode 0 Shift Register (Synchronous) Mode: Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are transmitted/ received (LSB first). The baud rate is fixed 16 the oscillator frequency. Mode 1 8-bit UART, Variable Baud Rate: 10 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in Special Function Register SCON. The baud rate is variable. Mode 2 9-bit UART, Fixed Baud Rate: 11 bits are transmitted (through TxD) or received (through RxD): start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On Transmit, the 9th data bit (TB8 in SCON) can be assigned the value of 0 or 1. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. On receive, the 9th data bit goes into RB8 in Special Function Register SCON, while the stop bit ignored. The baud rate is programmable to either 116 or 132 the oscillator frequency. P8xC591 Mode 3 9-bit UART, Variable Baud Rate: 11 bits are transmitted (through TxD) or received (through RxD): start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable. In all four modes, transmission is initiated by any instruction that uses S0BUF as a destination register. Reception is initiated in Mode 0 by the condition RI = 0 and REN = 1. Reception is initiated in the other modes by the incoming start bit if REN = 1. 14.1 Multiprocessor Communications Modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received. The 9th one goes into RB8. Then comes a stop bit. The port can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if RB8 = 1. This feature is enabled by setting bit SM2 in SCON. A way to use this feature in multiprocessor systems is as follows: When the master processor wants to transmit a block of data to one of several slaves, it first send out an address byte which indentifies the target slave. An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. With SM2 = 1, no slave will be interrupted by a data byte. An address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be coming. The slaves that weren't being addressed leave their SM2s set and go on about their business, ignoring the coming data bytes. SM2 has no effect in Mode 0, and in Mode 1 can be used to check the validity of the stop bit. In a Mode 1 reception, if SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is received. 14.2 Serial Port Control Register The serial port control and status register is the Special Function Register SCON, shown in Table 38, 40 and 41. This register contains not only the mode selection bits, but also the 9th data bit for transmit and receive (TB8 and RB8), and the serial port interrupt bits (TI and RI). S0BUF is the receive and transmit buffer of serial interface. Writing to S0BUF loads the transmit register and initiates transmission. Reading out S0BUF accesses a physically separate receive register. 1999 Aug 19 61 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 14.3 Baud Rate Generation P8xC591 There are several possibilities to generate the baud rate clock for the serial port depending on the mode in which it is operating. For clarification some terms regarding the difference between "baud rate clock" and "baud rate" should be mentioned. The serial interface requires a clock rate which is 16 times the baud rate for internal synchronization. Therefore, the baud rate generators have to provide a "baud rate clock" to the serial interface which - there 14.3.1 divided by 16 - results in the actual "baud rate". However, all formulas given in the following section already include the factor and calculate the final baud rate. Further, the abbreviation fCLK refers to the external clock frequency (oscillator or external input clock operation). The baud rate of the serial port is controlled by the two bits SPS and SMOD1 which are located in the Special Function Registers S0PSH and PCON. In SFRs S0PSH and S0PSL the prescaler load value of the internal baud rate generator can be programmed (see Table 38 to 43). INTERNAL BAUD RATE GENERATOR PRESCALER S0PSH, S0PSL Table 38 Internal Baud Rate Generator Prescaler Low Register S0PSL (address FAH) Prescaler load value 7 6 5 4 3 2 1 0 prescaler load value Table 39 Description of S0PSL bits BIT 7 to 0 SYMBOL - DESCRIPTION Baud reload low value. Lower 8 bits of the baud rate timer reload value. Table 40 Internal Baud Rate Generator Prescaler High Register S0PSH (address FBH) Prescaler higher nibble load value 7 SPS 6 - 5 - 4 - 3 2 1 0 higher nibble load value Table 41 Description of S0PSH bits BIT 7 SYMBOL SPS DESCRIPTION Baud rate generator enable. When set, the baud rate of serial interface is derived from the dedicated baud rate generator. When cleared (default after reset), baud rate is derived from the Timer 1 overflow rate. Reserved. Baud rate generator reload high value. Upper four bits of the baud rate timer value. 6 to 4 3 to 0 14.3.2 - - PCON FOR THE INTERNAL BAUD RATE GENERATOR Table 42 PCON (address 87H) Prescaler load value 7 SMOD1 6 SMOD0 5 (POF) 4 (WLE) 3 (GF1) 2 (GF0) 1 (PD) 0 (IDL) Table 43 Description of SMOD1 and SMOD0 bits BIT 7 6 5 to 0 1999 Aug 19 SYMBOL SMOD1 DESCRIPTION Double Baud rate. When set, the baud rate of serial interface is modes 1, 2, 3 is doubled. After reset this bit is cleared. SMOD0 Double Baud rate. Selects SM0/FE for SCON.7 bit. (POF) to (IDL) Description refer to Section 11.3.5 "Power Control Register (PCON)". 62 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 14.3.3 BAUD RATE GENERATION OVERVIEW OF OPTIONS P8xC591 Depending on the programmed operating mode different paths are selected for the baud rate clock generation. Figure 23 shows the dependencies of the serial port baud rate clock generation on the two control bits and from the mode which is selected in the Special Function Register SCON: handbook, full pagewidth 1 TIMER overflow S0PSH.7 (SPS) BAUD RATE GENERATOR SCON.7 SCON.6 (SM0/FE) mode 1 mode 3 PCON.7 (SMOD1) 0 1 /2 f CLK (S0PSH S0PSL) 0 1 BAUD RATE CLOCK mode 2 MHI024 /6 mode 0 only one mode can be selected Note: The switch configuration shows the reset state. Fig.23 Baud Rate Generation for the Serial Port. 1999 Aug 19 63 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 14.3.4 BAUD RATE IN MODE 0 14.3.7 P8xC591 USING THE INTERNAL BAUD RATE GENERATOR The baud rate in Mode 0 is fixed to: oscillator frequency Mode 0 baud rate = ------------------------------------------------------6 14.3.5 BAUD RATE IN MODE 2 The baud rate in Mode 2 depends on the value of bit SMOD1 in Special Function Register PCON. If SMOD1 = 0 (which is the value after reset), the baud rate is 132 of oscillator frequency. If SMOD1 = 1, the baud rate is 116 of the oscillator frequency: 2 Mode 2 baud rate = -------------------- x oscillator frequency 32 14.3.6 BAUD RATE IN MODE 1 AND 3 SMOD1 In Modes 1 and 3, the P8xC591 can use an internal baud rate generator for the serial port. To enable this feature, bit SPS (bit 7 of Special Function Register S0PSH) must be set. Bit SMOD1 (PCON.7) controls a divide-by-2 circuit which affect the input and output clock signal of the baud rate generator. After reset the divide-by-2 circuit is active and the resulting overflow output clock will be divided by 2. The input clock of the baud rate generator is fCLK. The baud rate generator consists of its own free running upward counting 12-bit timer. On overflow of this timer (next count step after counter value FFFH) there is an automatic 12-bit reload from the registers S0PSL and S0PSH. The lower 8 bits of the timer are reloaded from S0PSL, while the upper four bits are reloaded from bit 0 to 3 of register S0PSH. The baud rate timer is reloaded by writing to S0PSH. In these modes the baud rate is variable and can be generated alternatively by a baud rate generator or by Timer 1. handbook, full pagewidth BAUD RATE S0PSH .3 .2 .1 .0 S0PSL PCON.7 (SMOD1) f CLK input clock 12 BIT TIMER overflow /2 0 1 MHI025 BAUD RATE CLOCK Note: The switch configuration shows the reset state. Fig.24 Serial Port Input Clock when using the Baud Rate Generator. 1999 Aug 19 64 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller With the baud rate generator as clock source for the serial port in Mode 1 and Mode 3, the baud rate of can be determined as follows: Mode 1, 3 baud rate = 2 x osciillator frequency -------------------------------------------------------------------------------------------------------32 x (baud rate generator overflow rate) Baud rate generator overflow rate = 212 - S0PS with S0PS = S0PSH.3 - 0, S0PSL.7 - 0. S0PS: Baud Rate Generator Prescaler load value Table 47 lists baud rates and how they can be obtained from the Internal Baud Rate Generator. 14.3.8 USING TIMER 1 TO GENERATE BAUD RATES SMOD1 SMOD1 P8xC591 2 Mode 1, 3 baud rate = -------------------- x (timer 1 overflow rate) 32 The Timer 1 interrupt is usually disabled in this application. Timer 1 itself can be configured for either "timer" or "counter" operation, and in any of its operating modes. In most typical applications, it is configured for "timer" operation in the auto-reload (high nibble of TMOD = 0010B). In this case the baud rate is given by the formula: 2 x oscillator frequency Mode1, 3 baud rate = -----------------------------------------------------------------------------32 x 6 x ( 256 - ( TH1 ) ) Very low baud rates can be achieved with Timer 1 if leaving the Timer 1 interrupt enabled, configuring the timer to run as 16-bit timer (high nibble of TMOD = 0001B), and using the Timer 1 interrupt for a 16-bit software reload. Table 48 lists lower baud rates and how they can be obtained from Timer 1. SMOD1 In Mode 1 and 3 of the serial port also timer 1 can be used for generating baud rates. Then the baud rate is determined by the timer 1 overflow rate and the value of SMOD1 as follows: Table 44 Serial Port Control Register SCON (address) 7 SM0 6 SM1 5 SM2 4 REN 3 TB8 2 RB8 1 TI 0 RI Table 45 Description of S0PSH and S0PSL bits BIT 7 6 5 SYMBOL SM0 SM1 SM2 See Table 46. See Table 46. Enables the multiprocessor communication feature in Modes 2 and 3. In Mode 2 or 3, if SM2 is set to 1, then RI will not be activated if the received 9th data bit (RB8) is 0. In Mode 1, if SM2 = 1 then RI will not be activated if a valid stop bit was not received. In Mode 0, SM2 should be 0. Enables serial reception. Set by software to enable reception. Clear by software to disable reception. The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. In Modes 2 and 3, is the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received. In Mode 0, RB8 is not used. Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. Must be cleared by software. Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see SM2). Must be cleared by software. DESCRIPTION 4 3 2 1 REN TB8 RB8 TI 0 RI 1999 Aug 19 65 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller Table 46 Serial port mode select SM0 0 0 1 1 SM1 0 1 0 1 MODE Mode 0 Mode 1 Mode 2 Mode 3 DESCRIPTION Shift register 8-bit UART 9-bit UART 9-bit UART P8xC591 BAUD RATE 1 6 x fCLK x fCLK variable 1 or 1 32 16 variable Table 47 Internal baud rate timer generated baud rates BAUD RATE (KBits/s) 1000 750 500 250 250 38.4 38.4 19.2 9.6 4.8 0.3 0.11 INTERNAL BAUD RATE TIMER fCLK (MHz) 16 12 8 8 8 8 16 4 16 16 16 8 SPS 1 1 1 1 1 1 1 1 1 1 1 1 SMOD1 DEVIATION % 1 1 1 0 1 1 0 1 1 1 1 0 0 0 0 0 0 0.16 0.16 0.16 0.16 0.16 0.01 -0.01 MODE 1/3 1/3 1/3 1/3 1/3 1/3 1/3 1/3 1/3 1/3 1/3 1/3 RELOAD VALUE FFFh FFFh FFFh FFFh FFEh FF3h FF3h FF3h F98h F30h 2FBh 71Fh Table 48 Timer 1 generated baud rates BAUD RATE (KBits/s) 110 110 110 110 INTERNAL BAUD RATE TIMER fCLK (MHz) 16 12 4 4 SPS 0 0 0 0 SMOD1 DEVIATION % 1 0 1 0 0.01 0.03 -0.06 0.21 MODE 1 1 1 2 RELOAD VALUE FA15h FDC8h FE85h 43h 1999 Aug 19 66 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 14.4 More about UART Modes More About Mode 1 P8xC591 More About Mode 0 Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are transmitted/received: 8 data bits (LSB first). The baud rate is fixed a 16 the oscillator frequency. Figure 25 shows a simplified functional diagram of the serial port in Mode 0, and associated timing. Transmission is initiated by any instruction that uses S0BUF as a destination register. The "write to S0BUF" signal at S6P2 also loads a 1 into the 9th position of the transmit shift register and tells the TX Control block to commence a transmission. The internal timing is such that one full machine cycle will elapse between "write to S0BUF" and activation of SEND. SEND enables the output of the shift register to the alternate output function line of P3.0 and also enable SHIFT CLOCK to the alternate output function line of P3.1. SHIFT CLOCK is low during S3, S4, and S5 of every machine cycle, and high during S6, S1 and S2. At S6P2 of every machine cycle in which SEND is active, the contents of the transmit shift are shifted to the right one position. As data bits shift out to the right, zeros come in from the left. When the MSB of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9th position, is just to the left of the MSB, and all positions to the left of that contain zeros. This condition flags the TX Control block to do one last shift and then deactivate SEND and set T1. Both of these actions occur at S1P1 of the 10th machine cycle after "write to S0BUF". Reception is initiated by the condition REN = 1 and R1 = 0. At S6P2 of the next machine cycle, the RX Control unit writes the bits 11111110 to the receive shift register, and in the next clock phase activates RECEIVE. RECEIVE enable SHIFT CLOCK to the alternate output function line of P3.1. SHIFT CLOCK makes transitions at S3P1 and S6P1 of every machine cycle. At S6P2 of every machine cycle. At S6P2 of every machine cycle in which RECEIVE is active, the contents of the receive shift register are shifted to the left one position. The value that comes in from the right is the value that was sampled at the P3.0 pin at S5P2 of the same machine cycle. As data bits come in from the right, 1s shift out to the left. When the 0 that was initially loaded into the rightmost position arrives at the leftmost position in the shift register, it flags the RX Control block to do one last shift and load S0BUF. At S1P1 of the 10th machine cycle after the write to SCON that cleared RI, RECEIVE is cleared as RI is set. 1999 Aug 19 67 Ten bits are transmitted (through TxD), or received (through RxD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in SCON. In the 80C51 the baud rate is determined by the Timer 1 overflow rate. Figure 26 shows a simplified functional diagram of the serial port in Mode1, and associated timings for transmit receive. Transmission is initiated by any instruction that uses S0BUF as a destination register. The "write to S0BUF" signal also loads a1 into the 9th bit position of the transmit shift register and flags the TX Control unit that a transmission is requested. Transmission actually commences at S1P1 of the machine cycle following the next rollover in the divide-by-16 counter. (Thus, the bit times are synchronized to the divide-by-16 counter, not to the "write to S0BUF" signal.) The transmission begins with activation of SEND which puts the start bit at TxD. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to TxD. The first shift pulse occurs one bit time after that. As data bits shift out to the right, zeros are clocked in from the left. When the MSB of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9th position is just to the left of the MSB, and all positions to the left of that contain zeros. The condition flags the TX Control unit to do one last shift and then deactivate SEND and set TI. This occurs at the 10th divide-by-16 rollover after "write to S0BUF". Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established. When a transition is detected, the divide-by-16 counter is immediately reset, and 1 FFH is written into the input shift register. Resetting the divide-by-16 counter aligns its rollovers with the boundaries of the incoming bit times. The 16 states of the counter divide each bit time into 16ths. At the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of RxD. The value accepted is the value that was seen in at least 2 of the 3 samples. This is done for noise rejection. If the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. This is to provide rejection of false start bits. If the start bit proves valid, it shifted into the input shift register, and reception of the rest of the frame will proceed. Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller As data bits come in from the right, 1s shift out to the left. When the start bit arrives at the leftmost position in the shift register (which in Mode 1 is a 9-bit register), it flags the RX Control block to do one last shift, load S0BUF and RB8, and set RI. The signal to load S0BUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated: 1. RI = 0, and 2. Either SM2 = 0, or the received stop bit = 1. If either of these two conditions is not met, the received frame is irretrievably lost. If both conditions are met, the stop bit goes into RB8, the 8 data bits go into S0BUF, and RI is activated. At this time, whether the above conditions are met or not, the unit goes back to looking for a 1-to-0 transition in RxD. More About Modes 2 and 3 Eleven bits are transmitted (through TxD), or received (through RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmit, the 9th data bit (TB8) can be assigned the values of 0 or 1. On receive, the 9the data bit goes into RB8 in SCON. The baud rate is programmable to either 116 or 132 the oscillator frequency in Mode 2. Mode 3 may have a variable baud rate generated from Timer 1. Figure 27 show a functional diagram of the serial port in Modes 2 and 3. The receive portion is exactly the same as in Mode 1. The transmit portion differs from Mode 1 only in the 9th bit of the transmit shift register. Transmission is initiated by any instruction that uses S0BUF as a destination register. The "write to S0BUF" signal also loads TB8 into the 9th bit position of the transmit shift register and flags the TX Control unit that a transmission is requested. Transmission commences at S1P1 of the machine cycle following the next rollover in the divide-by-16 counter. (Thus, the bit times are synchronized to the divide-by-16 counter, not to the "write to SUB" signal). The transmission begins with activation of SEND, which puts the start bit at TxD. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to TxD. The first shift pulse occurs one bit time after that. The first shift clocks a 1 (the stop bit) into the 9th bit position of the shift register. Thereafter, only zeros are clocked in. Thus, as data bit shift out to the right, zeros are clocked in from the left. When TB8 is at the output position of the shift register, then the stop bit is just to the left of TB8, and all positions to the left of that contain zeros. This condition flags the TX Control unit to do one last shift P8xC591 and then deactivate SEND and set TI. This occurs at the 11th divide-by-16 rollover after "write to SUBF". Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established. When a transition is detected, the divide-by-16 counter is immediately reset, and 1FFH is written to the input shift register. At the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of R-D. The value accepted is the value that was seen in at least 2 of the 3 samples. If the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. As data bits come in from the right, 1s shift out to the left. When the start bit arrives at the leftmost position in the shift register (which in Modes 2 and 3 is a 9-bit register), it flags the RX Control block to do one last shift, load S0BUF and RB8, and set RI. The signal to load S0BUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated. 1. RI = 0, and 2. Either SM2 = 0, or the received 9th data bit = 1. If either of these conditions is not met, the received frame is irretrievably lost, and RI is not set. If both conditions are met, the received 9th data bit goes into RB8, and the first 8 data bits go into S0BUF. One bit time later, whether the above conditions were met or not, the unit goes back to looking for a 1-to-0 transition at the RxD input. 1999 Aug 19 68 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 handbook, full pagewidth 80C51 INTERNAL BUS write to SBUF D CL S Q SBUF RxD P3.0 Alt output function ZERO DETECTOR Start TX CONTROL S6 TX Clock T1 Shift Send serial port interrupt R1 RX CONTROL SHIFT CLOCK RX Clock REN RI Start LSB Receive TxD P3.1 Alt output function Shift 11111110 MSB INPUT SHIFT REGISTER shift RxD P3.0 Alt input function load SBUF LSB read SBUF SBUF MSB 80C51 INTERNAL BUS S4 . . S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1 ALE Write to SBUF Send Shift RxD (Data Out) TxD (Shift Clock) TI S3P1 S6P1 D0 D1 D2 D3 D4 D5 D6 D7 S6P2 Transmit Write to SCON (Clear RI) RI Receive Shift RxD (Data In) D0 S5P2 TxD (Shift Clock) MHI026 Receive D1 D2 D3 D4 D5 D6 D7 Fig.25 Serial Port Mode 0. 1999 Aug 19 69 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 handbook, full pagewidth TB8 80C51 INTERNAL BUS write to SBUF D CL S Q SBUF TxD ZERO DETECTOR Shift Start BAUD RATE CLOCK Data Send /16 TX CONTROL TX Clock T1 serial port interrupt /16 sample 1-to-0 TRANSITION DETECTOR RX Clock Start R1 load SBUF Shift 1FFH RX CONTROL BIT DETECTOR RxD INPUT SHIFT REGISTER (9 BITS) load SBUF shift SBUF read SBUF 80C51 INTERNAL BUS TX Clock write to SBUF Send Data Shift TxD TI Start bit D0 D1 D2 D3 D4 D5 D6 D7 Stop bit S1P1 Transmit /16 Reset RX Clock RxD Bit detector sample times Shift RI MHI027 Start bit D0 D1 D2 D3 D4 D5 D6 D7 Stop bit Receive Fig.26 Serial Port Mode 1. 1999 Aug 19 70 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 handbook, full pagewidth TB8 80C51 INTERNAL BUS write to SBUF D CL S Q SBUF TxD ZERO DETECTOR BAUD RATE CLOCK /16 Stop bit Shift Data Start gen. TX CONTROL Send TX Clock T1 serial port interrupt /16 sample 1-to-0 TRANSITION DETECTOR RX Clock Start R1 load SBUF Shift 1FFH RX CONTROL BIT DETECTOR RxD INPUT SHIFT REGISTER (9 BITS) load SBUF shift SBUF read SBUF 80C51 INTERNAL BUS TX Clock write to SBUF Send Data Shift TxD TI Stop bit gen. Start bit D0 D1 D2 D3 D4 D5 D6 D7 TB8 Stop bit S1P1 Transmit /16 Reset RX Clock RxD Bit detector sample times Shift RI MHI028 Start bit D0 D1 D2 D3 D4 D5 D6 D7 TB8 Stop bit Receive Fig.27 Serial Port Mode 2 and 3. 1999 Aug 19 71 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 14.5 Enhanced UART 14.5.1 P8xC591 AUTOMATIC ADDRESS RECOGNITION The UART operates in all of the usual modes that are described in the Section of Standard Serial Interface, 80C51-Based 8-Bit Microcontrollers. In addition the UART can perform framing error detect by looking for missing stop bits, and automatic address recognition. The UART also fully supports multiprocessor communication as does the standard 80C51 UART. When used for framing error detect the UART looks for missing stop bits in the communication. A missing bit will set the FE bit in the S0CON register. The FE bit shares the S0CON.7 bit with SM0 and the function of S0CON.7 is determined by PCON.6 (SMOD0) see Table 50. If SMOD0 is set then S0CON.7 functions as FE. S0CON.7 functions as SM0 when SMOD0 is cleared. When as FE S0CON.7 can only be cleared by software. Refer to Figure 25. Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. This feature is enabled by setting the SM2 bit in S0CON. In the 9 bit UART modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be automatically set when the received byte contains either the "Given" address or the "Broadcast" address. The 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. Automatic address recognition is shown in Figure 29. The 8 bit mode is called Mode 1. In this mode the RI flag will be set if SM2 is enabled and the information received has a valid stop bit following the 8 address bits and the information is either a Given or Broadcast address. 14.5.2 SERIAL PORT CONTROL REGISTER (S0CON) Table 49 Serial Port Control Register (address 98H) 7 SM0/FE 6 SM1 5 SM2 4 REN 3 TB8 2 RB8 1 TI 0 RI Table 50 Description of S0CON bits BIT 7 SYMBOL FE SM0 6 5 SM1 SM2 DESCRIPTION Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid frames but should be cleared by software. Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0), see Table 46. These bits are used to select the serial port mode; see Table 46. Enables the Automatic Address Recognition feature in Modes 2 and 3. If SM2 = 1, then RI will not be set unless the received 9th data bit (RB8) is a logic 1, indicating an address, and the received byte is a Given or Broadcast Address. In Mode 1, if SM2 = 1, then RI will not be activated unless a valid stop bit was not received, and the received byte is a Given or Broadcast Address. In Mode 0, SM2 should be a logic 0. Enables serial reception. Set by software to enable reception. Clear by software to disable reception. The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received. In Mode 0, RB8 is not used. Transmit Interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. Must be cleared by software. Receive Interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see SM2). Must be cleared by software. 72 4 3 2 1 REN TB8 RB8 TI 0 RI 1999 Aug 19 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 handbook, full pagewidth D0 START bit D1 D2 D3 D4 D5 D6 D7 D8 STOP only bit in MODE 2, 3 DATA byte Set FE BIT if STOP BIT is 0 (FRAMING ERROR) SM0 to UART MODE CONTROL SM0/FE SM1 SM2 REN TB8 RB8 TI RI SCON (98H) SMOD1 SMOD0 POF WLE GF1 GF0 PD IDL PCON (87H) MHI029 0 : S0CON.7 = SM0 1 : S0CON.7 = FE Fig.28 UART Framing Error Detection. handbook, full pagewidth D0 D1 D2 D3 D4 D5 D6 D7 D8 SM0 1 1 SM1 1 0 SM2 1 REN 1 TB8 X RB8 TI RI SCON (98H) RECEIVED ADDRESS D0 TO D7 PROGRAMMED ADDRESS COMPARATOR MHI030 In UART Mode 2 or Mode 3 and SM2 = 1: Interrupt if REN = 1, RB8 = 1 and "Received Address" = "Programmed Address" when own address received, clear SM2 to receive data bytes when all data bytes have been received: set SM2 to wait for next address. Fig.29 UART Multiprocessor Communication, Automatic Address Recognition. 1999 Aug 19 73 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller Mode 0 is the Shift Register mode and SM2 is ignored. Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses. All of the slaves may be contacted by using the Broadcast address. All of the slaves may be contacted by using the Broadcast address. Two Special Function Registers are used to define the slave's address, SADDR, and the address mask, SADEN. SADEN is used to define which bits in the SADDR are to be used and which bits are "don't care". The SADEN mask can be logically ANDed with the SADDR to create the "Given" address which the master will use for addressing each of the slaves. Use of the Given address allows multiple slaves to be recognized while excluding others. The following examples will help to show the versatility of this scheme: Slave 0 SADDR = SADEN = Given = SADDR = SADEN = Given = 1100 0000 1111 1101 1100 00X0 1100 0000 1111 1110 1100 000X P8xC591 In the above example the differentiation among the 3 Slaves is in the lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. Slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude Slave 2. The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. Zeros in this result are trended as don't cares. In most cases, interpreting the don't-cares as ones, the broadcast address will be FF hexadecimal. Upon reset SADDR (SFR address 0A9H) and SADEN (SFR address 0B9H) are leaded with 0s. This produces a given address of all "don't cares" as well as a Broadcast address of all "don't cares". This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard 80C51 type UART drivers which do not make use of this feature. 15 SIO1, I2C SERIAL IO The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to the bus. The main features of the bus are: * Bidirectional data transfer between masters and slaves * Multimaster bus (no central master) * Arbitration between simultaneously transmitting masters without corruption of serial data on the bus * Serial clock synchronization allows devices with different bit rates to communicate via one serial bus * Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer * The I2C bus may be used for test and diagnostic purposes The I/O pins P1.6 and P1.7 must be set to Open Drain (SCL and SDA). The 8xC591 on-chip I2C logic provides a serial interface that meets the I2C bus specification. The SIO1 logic handles bytes transfer autonomously. It also keeps track of serial transfers, and a status register (S1STA) reflects the status of SIO1 and the I2C bus. Slave 1 In the above example SADDR is the same and the SADEN data is used to differentiate between the two salves. Slave 0 requires as 0 in bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is ignored. A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. A unique address for Slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit 0 = 0 (for Slave 0) and bit 1 = 0 (for Slave 1). Thus, both could be addressed with 1100 0000. In a more complex system the following could be used to select Slaves 1 and 2 while excluding Slave 0: Slave 0 SADDR = SADEN = Given = SADDR = SADEN = Given = SADDR = SADEN = Given = 1100 0000 1111 1001 1100 0XX0 1110 0000 1111 1010 1110 0X0X 1110 0000 1111 1100 1110 00XX Slave 1 Slave 2 1999 Aug 19 74 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller The CPU interfaces to the I2C logic via the following four special function registers: S1CON (SIO1 control register), S1STA (SIO1 status register), S1DAT (SIO1 data register), and S1ADR (SIO1 slave address register). The SIO1 logic interfaces to the external I2C bus via two port 1 pins: P1.6/SCL (serial clock line) and P1.7/SDA (serial data line). A typical I2C bus configuration is shown in Figure 30, and Figure 31 shows how a data transfer is accomplished on the bus. Depending on the state of the direction bit (R/W), two types of data transfers are possible on the I2C bus: 1. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. 2. Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is transmitted by the master. The slave then returns an acknowledge bit. Next follows the data bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a not acknowledge is returned. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the I2C bus will not be released. 15.1 Modes of Operation P8xC591 2. Master Receiver Mode: The first byte transmitted contains the slave address of the transmitting device (7 bits) and the data direction bit. In this case the data direction bit (R/W) will be logic 1, and we say that an "R" is transmitted. Thus the first byte transmitted is SLA+R. Serial data is received via P1.7/SDA while P1.6/SCL outputs the serial clock. Serial data is received 8 bits at a time. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are output to indicate the beginning and end of a serial transfer. 3. Slave Receiver Mode: Serial data and the serial clock are received through P1.7/SDA and P1.6/SCL. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit. 4. Slave Transmitter Mode: The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit will indicate that the transfer direction is reversed. Serial data is transmitted via P1.7/SDA while the serial clock is input through P1.6/SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer. In a given application, SIO1 may operate as a master and as a slave. In the slave mode, the SIO1 hardware looks for its own slave address and the general call address. If one of these addresses is detected, an interrupt is requested. When the microcontroller wishes to become the bus master, the hardware waits until the bus is free before the master mode is entered so that a possible slave action is not interrupted. If bus arbitration is lost in the master mode, SIO1 switches to the slave mode immediately and can detect its own slave address in the same serial transfer. The on-chip SIO1 logic may operate in the following four modes: 1. Master Transmitter Mode: Serial data output through P1.7/SDA while P1.6/SCL outputs the serial clock. The first byte transmitted contains the slave address of the receiving device (7 bits) and the data direction bit. In this case the data direction bit (R/W) will be logic 0, and we say that a "W" is transmitted. Thus the first byte transmitted is SLA+W. Serial data is transmitted 8 bits at a time. After each byte is transmitted, an acknowledge bit is received. START and STOP conditions are output to indicate the beginning and the end of a serial transfer. 1999 Aug 19 75 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 handbook, full pagewidth VDD RP RP SDA SCL I2C-bus P1.7/SDA P1.6/SCL 8xC591 OTHER DEVICE WITH I2C INTERFACE OTHER DEVICE WITH I2C INTERFACE MHI031 Fig.30 Typical I2C Bus configuration. handbook, full pagewidth MSB STOP condition repeated START condition acknowledgment signal from receiver clock line held low while interrupts are serviced SDA slave address R/W direction bit acknowledgment signal from receiver SCL S START condition 1 2 7 8 9 ACK 1 2 3-8 9 ACK P/S repeated if more bytes are transferred MHI032 Fig.31 Data Transfer on the I2C Bus. 1999 Aug 19 76 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 15.2 SIO1 Implementation and Operation I2C 15.2.4 SHIFT REGISTER, S1DAT P8xC591 Figure 32 shows how the on-chip bus interface is implemented, and the following text describes the individual blocks. 15.2.1 INPUT FILTERS AND OUTPUT STAGES The input filters have I2C compatible input levels. If the input voltage is less than 1.5 V, the input logic level is interpreted as 0; if the input voltage is greater than 3.0 V, the input logic level is interpreted as 1. Input signals are synchronized with the internal clock (fCLK/4), and spikes shorter than three oscillator periods are filtered out. The output stages consist of open drain transistors that can sink 3 mA at VOUT < 0.4 V. These open drain outputs do have clamping diodes to VDD. Thus, precautions have to be considered, if a powered-down 8xC591 on one board clamps the I2C bus externally. 15.2.2 ADDRESS REGISTER, S1ADR This 8-bit special function register contains a byte of serial data to be transmitted or a byte which has just been received. Data in S1DAT is always shifted from right to left; the first bit to be transmitted is the MSB (bit 7) and, after a byte has been received, the first bit of received data is located at the MSB of S1DAT. While data is being shifted out, data on the bus is simultaneously being shifted in; S1DAT always contains the last byte present on the bus. Thus, in the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data in S1DAT. This 8-bit special function register may be loaded with the 7-bit slave address (7 most significant bits) to which SIO1 will respond when programmed as a slave transmitter or receiver. The LSB (GC) is used to enable general call address (00H) recognition. 15.2.3 COMPARATOR The comparator compares the received 7-bit slave address with its own slave address (7 most significant bits in S1ADR). It also compares the first received 8-bit byte with the general call address (00H). If an equality is found, the appropriate status bits are set and an interrupt is requested. 1999 Aug 19 77 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 handbook, full pagewidth 8 P1.7 S1ADR ADDRESS REGISTER INPUT FILTER P1.7/SDA OUTPUT STAGE S1DAT COMPARATOR SHIFT REGISTER ACK 8 INPUT FILTER P1.6/SCL OUTPUT STAGE TIMER 1 OVERFLOW P1.6 S1CON TIMING & CONTROL LOGIC SERIAL CLOCK GENERATOR 1/4 fOSC INTERRUPT CONTROL REGISTER 8 STATUS BITS STATUS DECODER S1STA STATUS REGISTER 8 MHI033 Fig.32 I2C Bus Interface Block Diagram. 1999 Aug 19 78 INTERNAL BUS ARBITRATION & SYNC LOGIC Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 15.2.5 ARBITRATION AND SYNCHRONIZATION LOGIC P8xC591 In the master transmitter mode, the arbitration logic checks that every transmitted logic 1 actually appears as a logic 1 on the I2C bus. If another device on the bus overrules a logic 1 and pulls the SDA line low, arbitration is lost, and SIO1 immediately changes from master transmitter to slave receiver. SIO1 will continue to output clock pulses (on SCL) until transmission of the current serial byte is complete. Arbitration may also be lost in the master receiver mode. Loss of arbitration in this mode can only occur while SIO1 is returning a not acknowledge: (logic 1) to the bus. Arbitration is lost when another device on the bus pulls this signal LOW. Since this can occur only at the end of a serial byte, SIO1 generates no further clock pulses. Figure 33 shows the arbitration procedure. The synchronization logic will synchronize the serial clock generator with the clock pulses on the SCL line from another device. If two or more master devices generate clock pulses, the mark duration is determined by the device that generates the shortest marks, and the space duration is determined by the device that generates the longest spaces. Figure 34 shows the synchronization procedure. A slave may stretch the space duration to slow down the bus master. The space duration may also be stretched for handshaking purposes. This can be done after each bit or after a complete byte transfer. SIO1 will stretch the SCL space duration after a byte has been transmitted or received and the acknowledge bit has been transferred. The serial interrupt flag (SI) is set, and the stretching continues until the serial interrupt flag is cleared. handbook, full pagewidth (1) (1) (2) (3) SDA SCL 1 2 3 4 8 9 ACK MHI034 (1) Another device transmits identical serial data. (2) Another device overrules a logic 1 (dotted line) transmitted by SIO1 (master) by pulling the SDA line low. Arbitration is lost, and SIO1 enters the slave receiver mode. (3) SIO1 is in the slave receiver mode but still generates clock pulses until the current byte has been transmitted. SIO1 will not generate clock pulses for the next byte. Data on SDA originates from the new master once it has won arbitration. Fig.33 Arbitration Procedure. 1999 Aug 19 79 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 handbook, full pagewidth SDA (1) (3) (1) SCL MHI035 (2) mark duration space duration (1) Another service pulls the SCL line low before the SIO "mask" duration is complete. The serial clock generator is immediately reset and commences with the "space" duration by pulling SCL low. (2) Another device still pulls the SCL line low after SIO1 releases SCL. The serial clock generator is forced into the wait state until the SCL line is released. (3) The SCL line is released, and the serial clock generator commences with the mark duration. Fig.34 Serial Clock Synchronization. 15.2.6 SERIAL CLOCK GENERATOR 15.2.9 STATUS DECODER AND STATUS REGISTER This programmable clock pulse generator provides the SCL clock pulses when SIO1 is in the master transmitter or master receiver mode. It is switched off when SIO1 is in a slave mode. The programmable output clock frequencies are: fCLK/120, fCLK/9600, and the Timer 1 overflow rate divided by eight. The output clock pulses have a 50% duty cycle unless the clock generator is synchronized with other SCL clock sources as described above. 15.2.7 TIMING AND CONTROL The timing and control logic generates the timing and control signals for serial byte handling. This logic block provides the shift pulses for S1DAT, enables the comparator, generates and detects start and stop conditions, receives and transmits acknowledge bits, controls the master and slave modes, contains interrupt request logic, and monitors the I2C bus status. 15.2.8 CONTROL REGISTER, S1CON The status decoder takes all of the internal status bits and compresses them into a 5-bit code. This code is unique for each I2C bus status. The 5-bit code may be used to generate vector addresses for fast processing of the various service routines. Each service routine processes a particular bus status. There are 26 possible bus states if all four modes of SIO1 are used. The 5-bit status code is latched into the five most significant bits of the status register when the serial interrupt flag is set (by hardware) and remains stable until the interrupt flag is cleared by software. The three least significant bits of the status register are always zero. If the status code is used as a vector to service routines, then the routines are displaced by eight address locations. Eight bytes of code is sufficient for most of the service routines (see the software example in this section). 15.2.10 THE FOUR SIO1 SPECIAL FUNCTION REGISTERS The microcontroller interfaces to SIO1 via four special function registers. These four SFRs (S1ADR, S1DAT, S1CON, and S1STA) are described individually in the following sections. This 7-bit special function register is used by the microcontroller to control the following SIO1 functions: start and restart of a serial transfer, termination of a serial transfer, bit rate, address recognition, and acknowledgment. 1999 Aug 19 80 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 15.2.10.1 The Address Register, S1ADR The CPU can read from and write to this 8-bit, directly addressable SFR. S1ADR is not affected by the SIO1 hardware. The contents of this register are irrelevant when SIO1 is in a master mode. In the slave modes, the seven most significant bits must be loaded with the microcontrollers own slave address, and, if the least Table 51 Address Register S1ADR (address DBH) 7 X 6 X 5 X 4 X 3 X 2 X 1 X P8xC591 significant bit is set, the general call address (00H) is recognized; otherwise it is ignored. The most significant bit corresponds to the first bit received from the I2C bus after a start condition. A logic 1 in S1ADR corresponds to a high level on the I2C bus, and a logic 0 corresponds to a low level on the bus. 0 GC Table 52 Description of S1ADR (DBH) bits BIT 7 to 1 0 SYMBOL X GC Own slave address. 0 = general call address is not recognized. 1 = general call address is recognized. acknowledge bit. The ACK flag is controlled by the SIO1 hardware and cannot be accessed by the CPU. Serial data is shifted through the ACK flag into S1DAT on the rising edges of serial clock pulses on the SCL line. When a byte has been shifted into S1DAT, the serial data is available in S1DAT, and the acknowledge bit is returned by the control logic during the ninth clock pulse. Serial data is shifted out from S1DAT via a buffer (BSD7) on the falling edges of clock pulses on the SCL line. When the CPU writes to S1DAT, BSD7 is loaded with the content of S1DAT.7, which is the first bit to be transmitted to the SDA line (see Figure 36). After nine serial clock pulses, the eight bits in S1DAT will have been transmitted to the SDA line, and the acknowledge bit will be present in ACK. Note that the eight transmitted bits are shifted back into S1DAT. DESCRIPTION 15.2.11 THE DATA REGISTER, S1DAT S1DAT contains a byte of serial data to be transmitted or a byte which has just been received. The CPU can read from and write to this 8-bit, directly addressable SFR while it is not in the process of shifting a byte. This occurs when SIO1 is in a defined state and the serial interrupt flag is set. Data in S1DAT remains stable as long as SI is set. Data in S1DAT is always shifted from right to left: the first bit to be transmitted is the MSB (bit 7), and, after a byte has been received, the first bit of received data is located at the MSB of S1DAT. While data is being shifted out, data on the bus is simultaneously being shifted in; S1DAT always contains the last data byte present on the bus. Thus, in the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data in S1DAT. S1DAT and the ACK flag form a 9-bit shift register which shifts in or shifts out an 8-bit byte, followed by an Table 53 Address Register S1DAT (address DAH) 7 SD7 6 SD6 5 SD5 4 SD4 3 SD3 2 SD2 1 SD1 0 SD0 Table 54 Description of S1DAT (DAH) bits BIT 7 to 0 SYMBOL SD7 to SD0 DESCRIPTION Eight bits to be transmitted or just received. A logic 1 in S1DAT corresponds to a high level on the I2C bus, and a logic 0 corresponds to a low level on the bus. Serial data shifts through S1DAT from right to left. Figure 35 shows how data in S1DAT is serially transferred to and from the SDA line. 1999 Aug 19 81 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 15.2.12 THE CONTROL REGISTER, S1CON P8xC591 The CPU can read from and write to this 8-bit, directly addressable SFR. Two bits are affected by the SIO1 hardware: the SI bit is set when a serial interrupt is requested, and the STO bit is cleared when a STOP condition is present on the I2C bus. The STO bit is also cleared when ENS1 = 0. Table 55 Address Register S1CON (address D8H) 7 CR2 6 ENS1 5 STA 4 STO 3 SI 2 AA 1 CR1 0 CR0 Table 56 Description of S1CON (D8H) bits BIT 7 6 5 SYMBOL CR2 ENS1 STA Clock rate bit 2, see Table 57. Enable serial I/O. ENS1 = 0: I2C I/O disabled and reset. ENS1 = 1: serial I/O enabled. START flag. When this bit is set in slave mode, the hardware checks the I2C-bus and generates a START condition if the bus is free or after the bus becomes free. If the device operates in master mode it will generate a repeated START condition. STOP flag. If this bit is set in a master mode a STOP condition is generated. A STOP condition detected on the I2C-bus clears this bit. This bit may also be set in slave mode in order to recover from an error condition. In this case no STOP condition is generated to the I2C-bus, but the hardware releases the SDA and SCL lines and switches to the not selected receiver mode. The STOP flag is cleared by the hardware. Serial Interrupt flag. This flag is set and an interrupt request is generated, after any of the following events occur: * A START condition is generated in master mode. * The own slave address has been received during AA = 1. * The general call address has been received while S1ADR.0 and AA = 1. * A data byte has been received or transmitted in master mode (even if arbitration is lost). * A data byte has been received or transmitted as selected slave. * A STOP or START condition is received as selected slave receiver or transmitter. While the SI flag is set, SCL remains LOW and the serial transfer is suspended. SI must be reset by software. 2 AA Assert Acknowledge flag. When this bit is set, an acknowledge is returned after any one of the following conditions: * Own slave address is received. * General call address is received (S1ADR.0 = 1). * A data byte is received, while the device is programmed to be a master receiver. * A data byte is received. while the device is a selected slave receiver. When the bit is reset, no acknowledge is returned. Consequently, no interrupt is requested when the own address or general call address is received. 1 0 CR1 CR0 Clock rate bits 1 and 0; see Table 57. DESCRIPTION 4 STO 3 SI 1999 Aug 19 82 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 15.2.12.1 ENS1, the SIO1 enable bit ENS1 = "0": When ENS1 is "0", the SDA and SCL input signals are ignored, SIO1 is in the not addressed slave state, and the STO bit in S1CON is forced to 0. No other bits are affected. ENS1 = "1": When ENS1 is 1, I2C is enabled. Note, that P1.6 and P1.7 have to set to Open Drain by writing the Port mode registers P1M1.x and P1M2.x bits 6 and 7 with a 1 (see Section 6.2 "Pin description"). ENS1 should not be used to temporarily release SIO1 from the I2C bus since, when ENS1 is reset, the I2C bus status is lost. The AA flag should be used instead (see description of the AA flag in the following text). In the following text, it is assumed that ENS1 = 1. P8xC591 15.2.12.3 STO, the STOP Flag STO = "1": When the STO bit is set while SIO1 is in a master mode, a STOP condition is transmitted to the I2C bus. When the STOP condition is detected on the bus, the SIO1 hardware clears the STO flag. In a slave mode, the STO flag may be set to recover from an error condition. In this case, no STOP condition is transmitted to the I2C bus. However, the SIO1 hardware behaves as if a STOP condition has been received and switches to the defined not addressed slave receiver mode. The STO flag is automatically cleared by hardware. If the STA and STO bits are both set, the a STOP condition is transmitted to the I2C bus if SIO1 is in a master mode (in a slave mode, SIO1 generates an internal STOP condition which is not transmitted). SIO1 then transmits a START condition. STO = "0": When the STO bit is reset, no STOP condition will be generated. 15.2.12.2 STA, the START flag STA = "1": When the STA bit is set to enter a master mode, the SIO1 hardware checks the status of the I2C bus and generates a START condition if the bus is free. If the bus is not free, then SIO1 waits for a STOP condition (which will free the bus) and generates a START condition after a delay of a half clock period of the internal serial clock generator. If STA is set while SIO1 is already in a master mode and one or more bytes are transmitted or received, SIO1 transmits a repeated START condition. STA may be set at any time. STA may also be set when SIO1 is an addressed slave. STA = "0": When the STA bit is reset, no START condition or repeated START condition will be generated. 1999 Aug 19 83 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 handbook, full pagewidth INTERNAL BUS SDA 8 BSD7 S1DAT ACK SCL SHIFT PULSES MHI036 Fig.35 Serial Input/Output Configuration. handbook, full pagewidth SDA D7 D6 D5 D4 D3 D2 D1 D0 A SCL SHIFT ACK & S1DAT SHIFT IN (2) (2) (2) (2) (2) (2) (2) (2) ACK A S1DAT (1) (2) (2) (2) (2) (2) (2) (2) (2) (1) SHIFT BSD7 SHIFT OUT D7 D6 D5 D4 D3 D2 D1 D0 (3) BSD7 loaded by the CPU MHI037 (1) Valid data in S1DAT. (2) Shifting data in S1DAT and ACK. (3) High level on SDA. Fig.36 Shift-in and Shift-out Timing. 1999 Aug 19 84 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 15.2.12.4 SI, the Serial Interrupt Flag SI = "1": When the SI flag is set, then, if the EA and ES1 (interrupt enable register) bits are also set, a serial interrupt is requested. SI is set by hardware when one of 25 of the 26 possible SIO1 states is entered. The only state that does not cause SI to be set is state F8H, which indicates that no relevant state information is available. While SI is set, the low period of the serial clock on the SCL line is stretched, and the serial transfer is suspended. A high level on the SCL line is unaffected by the serial interrupt flag. SI must be reset by software. SI = 0: When the SI flag is reset, no serial interrupt is requested, and there is no stretching of the serial clock on the SCL line. P8xC591 When SIO1 is in the not addressed slave mode, its own slave address and the general call address are ignored. Consequently, no acknowledge is returned, and a serial interrupt is not requested. Thus, SIO1 can be temporarily released from the I2C bus while the bus status is monitored. While SIO1 is released from the bus, START and STOP conditions are detected, and serial data is shifted in. Address recognition can be resumed at any time by setting the AA flag. If the AA flag is set when the parts own slave address or the general call address has been partly received, the address will be recognized at the end of the byte transmission. 15.2.12.6 CR0, CR1, and CR2, the Clock Rate Bits These three bits determine the serial clock frequency when SIO1 is in a master mode. The various serial rates are shown in Table 57. A 12.5 kHz bit rate may be used by devices that interface to the I2C bus via standard I/O port lines which are software driven and slow. 100kHz is usually the maximum bit rate and can be derived from a 16 MHz, 12 MHz, or a 6 MHz oscillator. A variable bit rate (0.5 kHz to 62.5 kHz) may also be used if Timer 1 is not required for any other purpose while SIO1 is in a master mode. The frequencies shown in Table 57 are unimportant when SIO1 is in a slave mode. In the slave modes, SIO1 will automatically synchronize with any clock frequency up to 100 kHz. 15.2.12.5 AA, the Assert Acknowledge flag AA = "1": If the AA flag is set, an acknowledge (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when: * The "own slave address" has been received * The general call address has been received while the general call bit (GC) in S1ADR is set * A data byte has been received while SIO1 is in the master receiver mode * A data byte has been received while SIO1 is in the addressed slave receiver mode AA = "0": if the AA flag is reset, a not acknowledge (high level to SDA) will be returned during the acknowledge clock pulse on SCL when: * A data has been received while SIO1 is in the master receiver mode * A data byte has been received while SIO1 is in the addressed slave receiver mode When SIO1 is in the addressed slave transmitter mode, state C8H will be entered after the last serial is transmitted (see Figure 40). When SI is cleared, SIO1 leaves state C8H, enters the not addressed slave receiver mode, and the SDA line remains at a high level. In state C8H, the AA flag can be set again for future address recognition. 1999 Aug 19 85 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 15.2.13 THE STATUS REGISTER, S1STA S1STA is an 8-bit read-only special function register. The three least significant bits are always zero. The five most significant bits contain the status code. There are 26 possible status codes. When S1STA contains F8H, no relevant state information is available and no serial Table 57 Serial clock rate CR2 0 0 0 0 1 1 1 1 Note CR1 0 0 1 1 0 0 1 1 CR0 0 1 0 1 0 1 0 1 BIT FREQUENCY (kHz) at fCLK 6 MHz 23 27 31 37 6.25 50 100 0.24 > 62.5 0 < 255 12 MHz 47 54 63 75 12.5 100 200 0.49 < 62.5 0 < 254 16 MHz 62.5 71 83.3 100 17 133(1) 267(1) 0.65 < 55.6 0 < 253 P8xC591 interrupt is requested. All other S1STA values correspond to defined SIO1 states. When each of these states is entered, a serial interrupt is requested (SI = "1"). A valid status code is present in S1STA one machine cycle after SI is set by hardware and is still present one machine cycle after SI has been reset by software. fCLK DIVIDED BY 256 224 192 160 960 120 60 96 x (256 (reload value Timer 1)) Reload value Timer 1 in Mode 2. 1. These frequencies exceed the upper limit of 100 kHz of the I2C-bus specification and cannot be used in an I2C-bus application. 15.2.14 MORE INFORMATION ON SIO1 OPERATING MODES The four operating modes are: * Master Transmitter * Master Receiver * Slave Receiver * Slave Transmitter Data transfers in each mode of operation are shown in Figures 37 to 40. These figures contain the following abbreviations: In Figures 37 to 40, circles are used to indicate when the serial interrupt flag is set. The numbers in the circles show the status code held in the S1STA register. At these points, a service routine must be executed to continue or complete the serial transfer. These service routines are not critical since the serial transfer is suspended until the serial interrupt flag is cleared by software. When a serial interrupt routine is entered, the status code in S1STA is used to branch to the appropriate service routine. For each status code, the required software action and details of the following serial transfer are given in Tables 61 to 65. Abbreviation Explanation S SLA R W A A Data P Start condition 7-bit slave address Read bit (high level at SDA) Write bit (low level at SDA) Acknowledge bit (low level at SDA) Not acknowledge bit (high level at SDA) 8-bit data byte Stop condition 15.2.14.1 Master Transmitter Mode: In the master transmitter mode, a number of data bytes are transmitted to a slave receiver (see Figure 37). Before the master transmitter mode can be entered, S1CON must be initialized as in Table 58. CR0, CR1, and CR2 define the serial bit rate. ENS1 must be set to logic 1 to enable SIO1. If the AA bit is reset, SIO1 will not acknowledge its own slave address or the general call address in the event of another device becoming 1999 Aug 19 86 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller master of the bus. In other words, if AA is reset, SIO0 cannot enter a slave mode. STA, STO, and SI must be reset. The master transmitter mode may now be entered by setting the STA bit using the SETB instruction. The SIO1 logic will now test the I2C bus and generate a start condition as soon as the bus becomes free. When a START condition is transmitted, the serial interrupt flag (SI) is set, and the status code in the status register (S1STA) will be 08H. This status code must be used to vector to an interrupt service routine that loads S1DAT with the slave address and the data direction bit (SLA+W). The Table 58 Address Register S1CON (address D8H) 7 CR2 bit rate 6 ENS1 1 5 STA 0 4 STO 0 3 SI 0 2 AA X 1 CR1 P8xC591 SI bit in S1CON must then be reset before the serial transfer can continue. When the slave address and the direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag (SI) is set again, and a number of status codes in S1STA are possible. There are 18H, 20H, or 38H for the master mode and also 68H, 78H, or B0H if the slave mode was enabled (AA = logic 1). The appropriate action to be taken for each of these status codes is detailed in Table 61. After a repeated start condition (state 10H). SIO1 may switch to the master receiver mode by loading S1DAT with SLA+R). 0 CR0 bit rate 15.2.14.2 Master Receiver Mode In the master receiver mode, a number of data bytes are received from a slave transmitter (see Figure 38). The transfer is initialized as in the master transmitter mode. When the start condition has been transmitted, the interrupt service routine must load S1DAT with the 7-bit slave address and the data direction bit (SLA+R). The SI bit in S1CON must then be cleared before the serial transfer can continue. When the slave address and the data direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag (SI) is set again, and a number of status codes in S1STA are possible. These are 40H, 48H, or 38H for the master mode and also 68H, 78H, or B0H if the slave mode was enabled (AA = logic 1). The appropriate action to be taken for each of these status codes is detailed in Table 62. ENS1, CR1, and CR0 are not affected by the serial transfer and are not referred to in Table 62. After a repeated start condition (state 10H), SIO1 may switch to the master transmitter mode by loading S1DAT with SLA+W. The upper 7 bits are the address to which SIO1 will respond when addressed by a master. If the LSB (GC) is set, SIO1 will respond to the general call address (00H); otherwise it ignores the general call address. CR0, CR1, and CR2 do not affect SIO1 in the slave mode. ENS1 must be set to logic 1 to enable SIO1. The AA bit must be set to enable SIO1 to acknowledge its own slave address or the general call address. STA, STO, and SI must be reset. When S1ADR and S1CON have been initialized, SIO1 waits until it is addressed by its own slave address followed by the data direction bit which must be "0" (W) for SIO1 to operate in the slave receiver mode. After its own slave address and the W bit have been received, the serial interrupt flag (I) is set and a valid status code can be read from S1STA. This status code is used to vector to an interrupt service routine, and the appropriate action to be taken for each of these status codes is detailed in Table 63. The slave receiver mode may also be entered if arbitration is lost while SIO1 is in the master mode (see status 68H and 78H). If the AA bit is reset during a transfer, SIO1 will return a not acknowledge (logic 1) to SDA after the next received data byte. While AA is reset, SIO1 does not respond to its own slave address or a general call address. However, the I2C bus is still monitored and address recognition may be resumed at any time by setting AA. This means that the AA bit may be used to temporarily isolate SIO1 from the I2C bus. 15.2.14.3 Slave Receiver Mode: In the slave receiver mode, a number of data bytes are received from a master transmitter (see Figure 39). To initiate the slave receiver mode, S1ADR and S1CON must be loaded as in Table 59. 1999 Aug 19 87 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller Table 59 Address Register S1ADR (DBH) (address 00H) 7 X 6 X 5 X 4 X own slave address Table 60 Address Register S1CON (D8H) (address 00H) 7 CR2 X 6 ENS1 1 5 STA 0 4 STO 0 3 SI 0 2 AA 1 1 CR1 X 3 X 2 X 1 X P8xC591 0 GC 0 CR0 X handbook, full pagewidth MT SUCCESSFUL TRANSMISSION TO A SLAVE RECEIVER S SLA W A DATA A P 08H 18H 28H NEXT TRANSFER STARTED WITH A REPEATED START CONDITION S SLA W 10H NOT ACKNOWLEDGE RECEIVED AFTER THE SLAVE ADDRESS A P R 20H TO MST/REC MODE ENTRY = MR A P NOT ACKNOWLEDGE RECEIVED AFTER A DATA BYTE 30H ARBITRATION LOST IN SLAVE ADDRESS OR DATA BYTE A or A CONTINUES 38H OTHER MST A or A CONTINUES 38H OTHER MST ARBITRATION LOST AND ADDRESSED AS SLAVE A OTHER MST CONTINUES 68H 78H 80H TO CORRESPONDING STATES IN SLAVE MODE FROM MASTER TO SLAVE FROM SLAVE TO MASTER DATA A ANY NUMBER OF DATA BYTES AND THEIR ASSOCIATED ACKNOWLEDGE BITS n THIS NUMBER (CONTAINED IN S1STA) CORRESPONDS TO A DEFINED STATE OF THE I2C-BUS MHI038 (SEE TABLE 61) Fig.37 Format and States in the Master Transmitter Mode. 1999 Aug 19 88 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 handbook, full pagewidth MR SUCCESSFUL RECEPTION FROM A SLAVE TRANSMITTER S SLA R A DATA A DATA A P 08H 40H 50H 58H NEXT TRANSFER STARTED WITH A REPEATED START CONDITION S SLA R 10H NOT ACKNOWLEDGE RECEIVED AFTER THE SLAVE ADDRESS A P W 48H TO MST/TRX MODE ENTRY = MT OTHER MST ARBITRATION LOST IN SLAVE ADDRESS OR ACKNOWLEDGE BIT A or A CONTINUES 38H A OTHER MST CONTINUES 38H ARBITRATION LOST AND ADDRESSED AS SLAVE A OTHER MST CONTINUES 68H 78H 80H TO CORRESPONDING STATES IN SLAVE MODE FROM MASTER TO SLAVE FROM SLAVE TO MASTER DATA A ANY NUMBER OF DATA BYTES AND THEIR ASSOCIATED ACKNOWLEDGE BITS n THIS NUMBER (CONTAINED IN S1STA) CORRESPONDS TO A DEFINED STATE OF THE I2C-BUS (SEE TABLE 62) MHI039 Fig.38 Format and States in the Master Receiver Mode. 1999 Aug 19 89 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 handbook, full pagewidth RECEPTION OF THE OWN SLAVE ADDRESS AND ONE OR MORE DATA BYTES ALL ARE ACKNOWLEDGED S SLA W A DATA A DATA A P or S 60H 80H 80H A0H LAST DATA BYTE RECEIVED IS NOT ACKNOWLEDGED A P or S 88H ARBITRATION LOST AS MST AND ADDRESSED AS SLAVE A 68H RECEPTION OF THE GENERAL CALL ADDRESS AND ONE OR MORE DATA BYTES GENERAL CALL A DATA A DATA P or S 70H 90H 90H A0H LAST DATA BYTE IS NOT ACKNOWLEDGED A P or S 98H ARBITRATION LOST AS MST AND ADDRESSED AS SLAVE BY GENERAL CALL A A 78H FROM MASTER TO SLAVE FROM SLAVE TO MASTER DATA A ANY NUMBER OF DATA BYTES AND THEIR ASSOCIATED ACKNOWLEDGE BITS n THIS NUMBER (CONTAINED IN S1STA) CORRESPONDS TO A DEFINED STATE OF THE I2C-BUS (SEE TABLE 63) MHI040 Fig.39 Format and States in the Slave Receiver Mode. 1999 Aug 19 90 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 RECEPTION OF THE OWN handbook, full pagewidth SLAVE ADDRESS AND TRANSMISSION OF ONE OR MORE DATA BYTES S SLA R A DATA A DATA A P or S A8H B8H C0H A ARBITRATION LOST AS MST AND ADDRESSED AS SLAVE B0H LAST DATA BYTE TRANSMITTED. SWITCHED TO NOT ADDRESSED SLAVE (AA BIT IN S1CON = "0") A All "1"s P or S FROM MASTER TO SLAVE C8H FROM SLAVE TO MASTER DATA A ANY NUMBER OF DATA BYTES AND THEIR ASSOCIATED ACKNOWLEDGE BITS MHI041 n SEE TABLE 64) THIS NUMBER (CONTAINED IN S1STA) CORRESPONDS TO A DEFINED STATE OF THE I2C-BUS. (SEE TABLE 9. Fig.40 Format and States of the Slave Transmitter Mode. 1999 Aug 19 91 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller Table 61 Master Transmitter Mode STATUS CODE (S1STA) 08H 10H STATUS OF THE I2C BUS AND SIO1 HARDWARE A START condition has been transmitted A repeated START condition has been transmitted SLA+W has been transmitted; ACK has been received APPLICATION SOFTWARE RESPONSE TO S1CON TO/FROM S1DAT STA Load SLA+W Load SLA+W or Load SLA+R Load data byte or no S1DAT action or no S1DAT action or no S1DAT action X X X 0 1 0 1 STO 0 0 0 0 0 1 1 SI 0 0 0 0 0 0 0 AA X X X X X X X P8xC591 NEXT ACTION TAKEN BY SIO1 HARDWARE SLA+W will be transmitted; ACK bit will received As above SLA+W will be transmitted; SIO1 will be switched to MST/REC mode Data byte will be transmitted; ACK bit will be received been received Repeated START will be transmitted; STOP condition will be transmitted; STO flag will be reset STOP condition followed by a START condition will be transmitted; STO flag will be reset Data byte will be transmitted; ACK will be received Repeated START will be transmitted; STOP condition will be transmitted; STO flag will be reset STOP condition followed by a START condition will be transmitted; STO flag will be reset Data byte will be transmitted; ACK bit will be received Repeated START will be transmitted; STOP condition will be transmitted; STO flag will be reset STOP condition followed by a START condition will be transmitted; STO flag will be reset Data byte will be transmitted; ACK bit will be received Repeated START will be transmitted; STOP condition will be transmitted; STO flag will be reset STOP condition followed by a START condition will be transmitted; STO flag will be reset I2C bus will be released; not addressed slave will be entered A START condition will be transmitted when the bus becomes free 18H 20H SLA+W has been transmitted; NOT ACK has been received Load data byte or no S1DAT action or no S1DAT action or no S1DAT action 0 1 0 1 0 0 1 1 0 0 0 0 X X X X 28H Data byte in S1DAT has been transmitted; ACK has been received Load data byte or no S1DAT action or no S1DAT action or no S1DAT action 0 1 0 1 0 0 1 1 0 0 0 0 X X X X 30H Data byte in S1DAT has been transmitted; NOT ACK has been received Load data byte or no S1DAT action or no S1DAT action or no S1DAT action 0 1 0 1 0 0 1 1 0 0 0 0 X X X X 38H Arbitration lost in SLA+R/W or Data bytes No S1DAT action or No S1DAT action 0 1 0 0 0 0 X X 1999 Aug 19 92 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller Table 62 Master Receiver Mode STATUS CODE (S1STA) 08H 10H STATUS OF THE I2C BUS AND SIO1 HARDWARE A START condition has been transmitted A repeated START condition has been transmitted Arbitration lost in NOT ACK bit APPLICATION SOFTWARE RESPONSE TO S1CON TO/FROM S1DAT STA Load SLA+WR Load SLA+R or Load SLA+W no S1DAT action or no S1DAT action 40H SLA+R has been transmitted; ACK has been received SLA+R has been transmitted; NOT ACK has been received no S1DAT action or no S1DAT action no S1DAT action or no S1DAT action or no S1DAT action X X X 0 1 0 0 1 0 1 STO 0 0 0 0 0 0 0 0 1 1 SI 0 0 0 0 0 0 0 0 0 0 AA X X X X X 0 1 X X X P8xC591 NEXT ACTION TAKEN BY SIO1 HARDWARE SLA+R will be transmitted; ACK bit will be received As above SLA+W will be transmitted; SIO1 will be switched to MST/TRX mode I2C bus will be released; SIO1 will enter a slave mode A START condition will be transmitted when the bus becomes free Data byte will be received; NOT ACK bit will be returned Data byte will be received; ACK bit will be returned Repeated START condition will be transmitted STOP condition will be transmitted; STO flag will be reset STOP condition followed by a START condition will be transmitted; STO flag will be reset Data byte will be received; NOT ACK bit will be returned Data byte will be received; ACK bit will be returned Repeated START condition will be transmitted STOP condition will be transmitted; STO flag will be reset STOP condition followed by a START condition will be transmitted; STO flag will be reset 38H 48H 50H Data byte has been received; NOT ACK has been returned Data byte has been received; ACK has been returned Read data byte or read data byte Read data byte or read data byte or read data byte 0 0 1 0 1 0 0 0 1 1 0 0 0 0 0 0 1 X X X 58H Table 63 Slave Receiver Mode STATUS CODE (S1STA) 60H STATUS OF THE I2C BUS AND SIO1 HARDWARE Own SLA+W has been received; ACK has been returned Arbitration lost in SLA+R/W as master; Own SLA+W has been received, ACK returned APPLICATION SOFTWARE RESPONSE TO S1CON TO/FROM S1DAT STA No S1DAT action or no S1DAT action No S1DAT action or no S1DAT action X X X X STO 0 0 0 0 SI 0 0 0 0 AA 0 1 0 1 Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned NEXT ACTION TAKEN BY SIO1 HARDWARE 68H 1999 Aug 19 93 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 STATUS CODE (S1STA) 70H STATUS OF THE I2C BUS AND SIO1 HARDWARE General call address (00H) has been received; ACK has been returned Arbitration lost in SLA+R/W as master; General call address has been received, ACK has been returned Previously addressed with own SLV address; DATA has been received; ACK has been returned Previously addressed with own SLA; DATA byte has been received; NOT ACK has been returned APPLICATION SOFTWARE RESPONSE TO S1CON TO/FROM S1DAT STA No S1DAT action or no S1DAT action No S1DAT action or no S1DAT action X X X X STO 0 0 0 0 SI 0 0 0 0 AA 0 1 0 1 Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Switched to not addressed SLV mode; no recognition of own SLA or General call address Switched to not addressed SLV mode; Own SLA will be recognized; General call address will be recognized if S1ADR.0 = logic 1 Switched to not addressed SLV mode; no recognition of own SLA or General call address. A START condition will be transmitted when the bus becomes free Switched to not addressed SLV mode; Own SLA will be recognized; General call address will be recognized if S1ADR.0 = logic 1. A START condition will be transmitted when the bus becomes free. Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Switched to not addressed SLV mode; no recognition of own SLA or General call address Switched to not addressed SLV mode; Own SLA will be recognized; General call address will be recognized if S1ADR.0 = logic 1 Switched to not addressed SLV mode; no recognition of own SLA or General call address. A START condition will be transmitted when the bus becomes free Switched to not addressed SLV mode; Own SLA will be recognized; General call address will be recognized if S1ADR.0 = logic 1. A START condition will be transmitted when the bus becomes free. NEXT ACTION TAKEN BY SIO1 HARDWARE 78H 80H Read data byte or read data byte X X 0 0 0 0 0 1 88H Read data byte or 0 0 0 0 read data byte or 0 0 0 1 read data byte or 1 0 0 0 read data byte 1 0 0 1 90H Previously addressed with General Call; DATA byte has been received; ACK has been returned Previously addressed with General Call; DATA byte has been received; NOT ACK has been returned Read data byte or read data byte Read data byte or X X 0 0 0 0 0 0 0 0 1 0 98H read data byte or 0 0 0 1 read data byte or 1 0 0 0 read data byte 1 0 0 1 1999 Aug 19 94 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 STATUS CODE (S1STA) A0H STATUS OF THE I2C BUS AND SIO1 HARDWARE A STOP condition or repeated START condition has been received while still addressed as SLV/REC or SLV/TRX APPLICATION SOFTWARE RESPONSE TO S1CON TO/FROM S1DAT STA No STDAT action or 0 STO 0 SI 0 AA 0 Switched to not addressed SLV mode; no recognition of own SLA or General call address Switched to not addressed SLV mode; Own SLA will be recognized; General call address will be recognized if S1ADR.0 = logic 1 Switched to not addressed SLV mode; no recognition of own SLA or General call address. A START condition will be transmitted when the bus becomes free Switched to not addressed SLV mode; Own SLA will be recognized; General call address will be recognized if S1ADR.0 = logic 1. A START condition will be transmitted when the bus becomes free. NEXT ACTION TAKEN BY SIO1 HARDWARE No STDAT action or 0 0 0 1 No STDAT action or 1 0 0 0 No STDAT action 1 0 0 1 Table 64 Slave Transmitter Mode STATUS CODE (S1STA) A8H STATUS OF THE I2C BUS AND SIO1 HARDWARE Own SLA+R has been received; ACK has been returned Arbitration lost in SLA+R/W as master; Own SLA+R has been received, ACK has been returned Data byte in S1DAT has been transmitted; ACK has been received Data byte in S1DAT has been transmitted; NOT ACK has been received APPLICATION SOFTWARE RESPONSE TO S1CON TO/FROM S1DAT STA Load data byte or load data byte Load data byte or load data byte X X X X STO 0 0 0 0 SI 0 0 0 0 AA 0 1 0 1 Last data byte will be transmitted and ACK bit will be received Data byte will be transmitted; ACK will be received Last data byte will be transmitted and ACK bit will be received Data byte will be transmitted; ACK bit will be received Last data byte will be transmitted and ACK bit will be received Data byte will be transmitted; ACK bit will be received Switched to not addressed SLV mode; no recognition of own SLA or General call address Switched to not addressed SLV mode; Own SLA will be recognized; General call address will be recognized if S1ADR.0 = logic 1 Switched to not addressed SLV mode; no recognition of own SLA or General call address. A START condition will be transmitted when the bus becomes free Switched to not addressed SLV mode; Own SLA will be recognized; General call address will be recognized if S1ADR.0 = logic 1. A START condition will be transmitted when the bus becomes free. NEXT ACTION TAKEN BY SIO1 HARDWARE B0H B8H Load data byte or load data byte No S1DAT action or X X 0 0 0 0 0 0 0 0 1 0 C0H no S1DAT action or 0 0 0 1 no S1DAT action or 1 0 0 0 no S1DAT action 1 0 0 1 1999 Aug 19 95 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 STATUS CODE (S1STA) C8H STATUS OF THE I2C BUS AND SIO1 HARDWARE Last data byte in S1DAT has been transmitted (AA = 0); ACK has been received APPLICATION SOFTWARE RESPONSE TO S1CON TO/FROM S1DAT STA No S1DAT action or 0 STO 0 SI 0 AA 0 Switched to not addressed SLV mode; no recognition of own SLA or General call address Switched to not addressed SLV mode; Own SLA will be recognized; General call address will be recognized if S1ADR.0 = logic 1 Switched to not addressed SLV mode; no recognition of own SLA or General call address. A START condition will be transmitted when the bus becomes free Switched to not addressed SLV mode; Own SLA will be recognized; General call address will be recognized if S1ADR.0 = logic 1. A START condition will be transmitted when the bus becomes free. NEXT ACTION TAKEN BY SIO1 HARDWARE no S1DAT action or 0 0 0 1 no S1DAT action or 1 0 0 0 no S1DAT action 1 0 0 1 Table 65 Miscellaneous States STATUS CODE (S1STA) F8H STATUS OF THE I2C BUS AND SIO1 HARDWARE No relevant state information available; SI =0 Bus error during MST or selected slave modes, due to an illegal START or STOP condition. State 00H can also occur when interference causes SIO1 to enter an undefined state. APPLICATION SOFTWARE RESPONSE TO S1CON TO/FROM S1DAT STA No S1DAT action STO SI AA Wait or proceed current transfer No S1CON action NEXT ACTION TAKEN BY SIO1 HARDWARE 00H No S1DAT action 0 1 0 X Only the internal hardware is affected in the MST or addressed SLV modes. In all cases, the bus is released and SIO1 is switched to the not addressed SLV mode. STO is reset. 1999 Aug 19 96 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 15.2.14.4 Slave Transmitter Mode In the slave transmitter mode, a number of data bytes are transmitted to a master receiver (see Figure 40). Data transfer is initialized as in the slave receiver mode. When S1ADR and S1CON have been initialized, SIO1 waits until it is addressed by its own slave address followed by the data direction bit which must be "1" (R) for SIO1 to operate in the slave transmitter mode. After its own slave address and the R bit have been received, the serial interrupt flag (SI) is set and a valid status code can be read from S1STA. This status code is used to vector to an interrupt service routine, and the appropriate action to be taken for each of these status codes is detailed in Table 64. The slave transmitter mode may also be entered if arbitration is lost while SIO1 is in the master mode (see state B0H). If the AA bit is reset during a transfer, SIO1 will transmit the last byte of the transfer and enter state C0H or C8H. SIO1 is switched to the not addressed slave mode and will ignore the master receiver if it continues the transfer. Thus the master receiver receives all 1s as serial data. While AA is reset, SIO1 does not respond to its own slave address or a general call address. However, the I2C bus is still monitored, and address recognition may be resumed at any time by setting AA. This means that the AA bit may be used to temporarily isolate SIO1 from the I2C bus. 15.2.15 SOME SPECIAL CASES P8xC591 The SIO1 hardware has facilities to handle the following special cases that may occur during a serial transfer: Simultaneous Repeated START Conditions from Two Masters. A repeated START condition may be generated in the master transmitter or master receiver modes. A special case occurs if another master simultaneously generates a repeated START condition (see Figure 41). Until this occurs, arbitration is not lost by either master since they were both transmitting the same data. If the SIO1 hardware detects a repeated START condition on the I2C bus before generating a repeated START condition itself, it will release the bus, and no interrupt request is generated. If another master frees the bus by generating a STOP condition, SIO1 will transmit a normal START condition (state 08H), and a retry of the total serial data transfer can commence. 15.2.15.1 Data Transfer after loss of Arbitration Arbitration may be lost in the master transmitter and master receiver modes (see Figure 33). Loss of arbitration is indicated by the following states in S1STA; 38H, 68H, 78H, and B0H (see Figures 37 and 38). If the STA flag in S1CON is set by the routines which service these states, then, if the bus is free again, a START condition (state 08H) is transmitted without intervention by the CPU, and a retry of the total serial transfer can commence. 15.2.14.5 Miscellaneous States There are two S1STA codes that do not correspond to a defined SIO1 hardware state (see Table 65). These are discussed below. S1STA = F8H: This status code indicates that no relevant information is available because the serial interrupt flag, SI, is not yet set. This occurs between other states and when SIO1 is not involved in a serial transfer. S1STA = 00H: This status code indicates that a bus error has occurred during an SIO1 serial transfer. A bus error is caused when a START or STOP condition occurs at an illegal position in the format frame. Examples of such illegal positions are during the serial transfer of an address byte, a data byte, or an acknowledge bit. A bus error may also be caused when external interference disturbs the internal SIO1 signals. When a bus error occurs, SI is set. To recover from a bus error, the STO flag must be set and SI must be cleared. This causes SIO1 to enter the not addressed slave mode (a defined state) and to clear the STO flag (no other bits in S1CON are affected). The SDA and SCL lines are released (a STOP condition is not transmitted). 15.2.15.2 Forced Access to the I2C bus In some applications, it may be possible for an uncontrolled source to cause a bus hang-up. In such situations, the problem may be caused by interference, temporary interruption of the bus or a temporary short-circuit between SDA and SCL. If an uncontrolled source generates a superfluous START or masks a STOP condition, then the I2C bus stays busy indefinitely. If the STA flag is set and bus access is not obtained within a reasonable amount of time, then a forced access to the I2C bus is possible. This is achieved by setting the STO flag while the STA flag is still set. No STOP condition is transmitted. The SIO1 hardware behaves as if a STOP condition was received and is able to transmit a START condition. The STO flag is cleared by hardware (see Figure 42). 1999 Aug 19 97 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 handbook, full pagewidth S SLA W A DATA A S OTHER MST CONTINUES P S SLA 08H 18H 28H 08H OTHER MASTER SENDS REPEATED START CONDITION EARLIER RETRY MHI042 Fig.41 Simultaneous repeated START conditions from 2 Masters. handbook, full pagewidth time limit STA FLAG STO FLAG SDA LINE SCL LINE MHI043 start condition Fig.42 Forces access to a busy I2C bus. 1999 Aug 19 98 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 15.2.15.3 I2C bus obstructed by a low level on SCL and SDA An I2C bus hang-up occurs if SDA or SCL is pulled LOW by an uncontrolled source. If the SCL line is obstructed (pulled LOW) by a device on the bus, no further serial transfer is possible, and the SIO1 hardware cannot resolve this type of problem. When this occurs, the problem must be resolved by the device that is pulling the SCL bus line LOW. If the SDA line is obstructed by another device on the bus (e.g., a slave device out of bit synchronization), the problem can be solved by transmitting additional clock pulses on the SCL line (see Figure 43). The SIO1 hardware transmits additional clock pulses when the STA flag is set, but no START condition can be generated because the SDA line is pulled LOW while the I2C bus is considered free. The SIO1 hardware attempts to generate a START condition after every two additional clock pulses on the SCL line. When the SDA line is eventually released, a normal START condition is transmitted, state 08H is entered, and the serial transfer continues. P8xC591 If a forced bus access occurs or a repeated START condition is transmitted while SDA is obstructed (pulled LOW), the SIO1 hardware performs the same action as described above. In each case, state 08H is entered after a successful START condition is transmitted and normal serial transfer continues. Note that the CPU is not involved in solving these bus hang-up problems. 15.2.15.4 Bus error A bus error occurs when a START or STOP condition is present at an illegal position in the format frame. Examples of illegal positions are during the serial transfer of an address byte, a data or an acknowledge bit. The SIO1 hardware only reacts to a bus error when it is involved in a serial transfer either as a master or an addressed slave. When a bus error is detected, SIO1 immediately switches to the not addressed slave mode, releases the SDA and SCL lines, sets the interrupt flag, and loads the status register with 00H. This status code may be used to vector to a service routine which either attempts the aborted serial transfer again or simply recovers from the error condition as shown in Table 65. handbook, full pagewidth STA FLAG (2) (1) (1) (3) SDA LINE SCL LINE start condition MHI044 (1) Unsuccessful attempt to send a Start condition. (2) SDA line released. (3) Successful attempt to send a Start condition; state D8H is centered. Fig.43 Recovering from a bus obstruction caused by a low level on SDA. 1999 Aug 19 99 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 15.3 Software Examples of SIO1 Service Routines 15.3.2 SIO1 INTERRUPT ROUTINE P8xC591 This section consists of a software example for: * Initialization of SIO1 after a RESET * Entering the SIO1 interrupt routine * The 26 state service routines for the - Master transmitter mode - Master receiver mode - Slave receiver mode - Slave transmitter mode 15.3.1 INITIALIZATION When the SIO1 interrupt is entered, the PSW is first pushed on the stack. Then S1STA and HADD (loaded with the high-order address byte of the 26 service routines by the initialization routine) are pushed on to the stack. S1STA contains a status code which is the lower byte of one of the 26 service routines. The next instruction is RET, which is the return from subroutine instruction. When this instruction is executed, the high and low order address bytes are popped from stack and loaded into the program counter. The next instruction to be executed is the first instruction of the state service routine. Seven bytes of program code (which execute in eight machine cycles) are required to branch to one of the 26 state service routines. In the initialization routine, SIO1 is enabled for both master and slave modes. For each mode, a number of bytes of internal data RAM are allocated to the SIO to act as either a transmission or reception buffer. In this example, 8 bytes of internal data RAM are reserved for different purposes. The data memory map is shown in Figure 44. The initialization routine performs the following functions: * S1ADR is loaded with the parts own slave address and the general call bit (GC) * P1.6 and P1.7 bit latches are loaded with logic 1s * RAM location HADD is loaded with the high-order address byte of the service routines * The SIO1 interrupt enable and interrupt priority bits are set * The slave mode is enabled by simultaneously setting the ENS1 and AA bits in S1CON and the serial clock frequency (for master modes) is defined by loading CR0 and CR1 in S1CON. The master routines must be started in the main program. The SIO1 hardware now begins checking the I2C bus for its own slave address and general call. If the general call or the own slave address is detected, an interrupt is requested and S1STA is loaded with the appropriate state information. The following text describes a fast method of branching to the appropriate service routine. SI PUSH PSW PUSH S1STA PUSH HADD RET Save PSW Push status code (low order address byte) Push high order address byte Jump to state service routine The state service routines are located in a 256-byte page of program memory. The location of this page is defined in the initialization routine. The page can be located anywhere in program memory by loading data RAM register HADD with the page number. Page 01 is chosen in this example, and the service routines are located between addresses 0100H and 01FFH. 15.3.3 THE STATE SERVICE ROUTINE The state service routines are located 8 bytes from each other. Eight bytes of code are sufficient for most of the service routines. A few of the routines require more than 8 bytes and have to jump to other locations to obtain more bytes of code. Each state routine is part of the SIO1 interrupt routine and handles one of the 26 states. It ends with a RETI instruction which causes a return to the main program. 1999 Aug 19 100 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 handbook, full pagewidth SPECIAL FUNCTION REGISTERS S1ADR S1DAT S1STA S1CON CR2 ENS1 STA ST0 SI 0 AA 0 CR1 GC DB DA 0 CR0 D9 D8 PSW D0 IPO PS1 B8 IEN0 EA ES1 AB P1 P1.7 P1.6 90 80 INTERNAL DATA RAM 7F BACKUP NUMBYTMST SLA HADD STD ORIGINAL VALUE OF NUMBYTMST NUMBER OF BYTES AS MASTER SLA + R/W TO BE TRANSMITTED TO SLA HIGHER ADDRESS BYTE INTERRUPT ROUTINE SLAVE TRANSMITTER DATA RAM 53 52 51 50 4F 48 SLAVE RECEIVER DATA RAM SRD MASTER RECEIVER DATA RAM MRD MASTER TRANSMITTER DATA RAM MTD 40 38 30 R1 R0 19 18 00 MHI045 Fig.44 SIO1 Data Memory Map. 1999 Aug 19 101 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 15.3.4 MASTER TRANSMITTER AND MASTER RECEIVER MODES P8xC591 The master mode is entered in the main program. To enter the master transmitter mode, the main program must first load the internal data RAM with the slave address, data bytes, and the number of data bytes to be transmitted. To enter the master receiver mode, the main program must first load the internal data RAM with the slave address and the number of data bytes to be received. The R/W bit determines whether SIO1 operates in the master transmitter or master receiver mode. Master mode operation commences when the STA bit in S1CION is set by the SETB instruction and data transfer is controlled by the master state service routines in accordance with Table 61, Table 62, Figure 37 and Figure 38. In the example below, 4 bytes are transferred. There is no repeated START condition. In the event of lost arbitration, the transfer is restarted when the bus becomes free. If a bus error occurs, the I2C bus is released and SIO1 enters the not selected slave receiver mode. If a slave device returns a not acknowledge, a STOP condition is generated. A repeated START condition can be included in the serial transfer if the STA flag is set instead of the STO flag in the state service routines vectored to by status codes 28H and 58H. Additional software must be written to determine which data is transferred after a repeated START condition. 15.3.5 SLAVE TRANSMITTER AND SLAVE RECEIVER MODES In the slave receiver mode, a maximum of 8 received data bytes can be stored in the internal data RAM. A maximum of 8 bytes ensures that other RAM locations are not overwritten if a master sends more bytes. If more than 8 bytes are transmitted, a not acknowledge is returned, and SIO1 enters the not addressed slave receiver mode. A maximum of one received data byte can be stored in the internal data RAM after a general call address is detected. If more than one byte is transmitted, a not acknowledge is returned and SIO1 enters the not addressed slave receiver mode. In the slave transmitter mode, data to be transmitted is obtained from the same locations in the internal data RAM that were previously loaded by the main program. After a not acknowledge has been returned by a master receiver device, SIO1 enters the not addressed slave mode. 15.3.6 ADAPTING THE SOFTWARE FOR DIFFERENT APPLICATIONS The following software example shows the typical structure of the interrupt routine including the 26 state service routines and may be used as a base for user applications. If one or more of the four modes are not used, the associated state service routines may be removed but, care should be taken that a deleted routine can never be invoked. This example does not include any time-out routines. In the slave modes, time-out routines are not very useful since, in these modes, SIO1 behaves essentially as a passive device. In the master modes, an internal timer may be used to cause a time-out if a serial transfer is not complete after a defined period of time. This time period is defined by the system connected to the I2C bus. After initialization, SIO1 continually tests the I2C bus and branches to one of the slave state service routines if it detects its own slave address or the general call address (see Table 63, Table 64, Figure 39, and Figure 40). If arbitration was lost while in the master mode, the master mode is restarted after the current transfer. If a bus error occurs, the I2C bus is released and SIO1 enters the not selected slave receiver mode. 1999 Aug 19 102 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller SI01 EQUATE LIST LOC OBJ SOURCE P8xC591 !***************************************************************************************************************************** ! LOCATIONS OF THE SI01 SPECIAL FUNCTION REGISTERS! !***************************************************************************************************************************** 00D8 00D9 00DA 00DB 00A8 00B8 S1CON S1STA S1DAT S1ADR IEN0 IP0 -0xd8 -0xd9 -0xda -0xdb -0xa8 02b8 !***************************************************************************************************************************** ! BIT LOCATIONS !***************************************************************************************************************************** 00DD 00BD STA SI01HP -0xdd -0xbd ! STA bit in S1CON ! IP0, SI01 Priority bit !***************************************************************************************************************************** ! IMMEDIATE DATA TO WRITE INTO REGISTER S1CON !***************************************************************************************************************************** 00D5 00C5 00C1 00E5 ENS1_NOTSTA_STO_NOTSI_AA_CR0 ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0 ENS1_NOTSTA_NOTSTO_NOTSI_NOTAA_CR0 ENS1_STA_NOTSTO_NOTSI_AA_CR0 -0xd5 -0xc5 -0xc1 -0xe5 ! Generates STOP ! (CR0 = 100kHz) ! Releases BUS and ACK ! ! Releases BUS and ! NOT ACK ! Releases BUS and set ! STA !***************************************************************************************************************************** ! GENERAL IMMEDIATE DATA !***************************************************************************************************************************** 0031 00A0 0001 00C0 00C1 0018 OWNSLA ENSI01 PAG1 SLAW SLAR SELRB3 -0x31 -0xa0 -0x01 -0xc0 -0xc1 -0x18 ! Own SLA+General Call ! must be written into S1ADR ! EA+ES1, enable SIO1 interrupt ! must be written into IEN0 ! select PAG1 as HADD ! SLA+W to be transmitted ! SLA+R to be transmitted ! Select Register Bank 3 1999 Aug 19 103 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 LOC OBJ SOURCE !***************************************************************************************************************************** ! LOCATIONS IN DATA RAM !***************************************************************************************************************************** 0030 0038 0040 0048 0053 MTD MRD SRD STD BACKUP -0x30 -0x38 -0x40 -0x48 -0x53 ! MST/TRX/DATA base address ! MST/REC/DATA base address ! SLV/REC/DATA base address ! SLV/TRX/DATA base address ! Backup from NUMBYTMST ! To restore NUMBYTMST in case ! of an Arbitration Loss. ! Number of bytes to transmit ! or receive as MST. ! Contains SLA+R/W to be ! transmitted. ! High Address byte for STATE 0f ! till STATE 25. 0052 0051 0050 NUMBYTMST SLA HADD -0x52 -0x51 -0x50 !***************************************************************************************************************************** ! INITIALIZATION ROUTINE ! Example to initialize IIC Interface as slave receiver or slave transmitter and start a MASTER TRANSMIT ! or a MASTER RECEIVE function. 4 bytes will be transmitted or received. !***************************************************************************************************************************** .sect .base 0000 4100 .sect .base INIT: initial 0x200 mov setb setb mov orl clr mov S1ADR,#OWNSLA P1(6) P1(7) HADD,#PAG1 ! Load own SLA + enable ! general call recognition ! P1.6 High level. ! P1.7 High level. strt 0x00 ajmp INIT ! RESET 0200 0203 0205 0207 020A 020D 020F 75DB31 D296 D297 755001 43A8A0 C2BD 75D8C5 IEN0,#ENSI01 ! Enable SI01 interrupt SI01HP ! SI01 interrupt low priority S1CON, #ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0 ! Initialize SLV funct. !***************************************************************************************************************************** ! START MASTER TRANSMIT FUNCTION !***************************************************************************************************************************** 0212 0215 0218 755204 7551C0 D2DD mov mov setb NUMBYTMST,#0x4 SLA,#SLAW STA ! Transmit 4 bytes. ! SLA+W, Transmit funct. ! set STA in S1CON! !***************************************************************************************************************************** ! START MASTER RECEIVE FUNCTION !***************************************************************************************************************************** 021A 021D 0220 755204 7551C1 D2DD mov mov setb NUMBYTMST,#0x4 SLA,#SLAR STA ! Receive 4 bytes. ! SLA+R, Receive funct. ! set STA in S1CON 1999 Aug 19 104 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 LOC OBJ SOURCE !***************************************************************************************************************************** ! SI01 INTERRUPT ROUTINE !***************************************************************************************************************************** .sect .base intvec 0x00 ! SI01 interrupt vector ! S1STA and HADD are pushed onto the stack. ! They serve as return address for the RET instruction. ! The RET instruction sets the Program Counter to address HADD, ! S1STA and jumps to the right subroutine. 002B 002D 002F 0031 C0D0 C0D9 C050 22 push push push ret psw S1STA HADD ! JMP to address HADD,S1STA. ! save psw !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : 00, Bus error. ! ACTION : Enter not addressed SLV mode and release bus. STO reset. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect .base 0100 0103 0105 75D8D5 D0D0 32 st0 0x100 mov pop reti S1CON,#ENS1_NOTSTA_STO_NOTSI_AA_CR0 psw ! clr SI ! set STO,AA !***************************************************************************************************************************** ! MASTER STATE SERVICE ROUTINES !***************************************************************************************************************************** !***************************************************************************************************************************** ! State 08 and State 10 are both for MST/TRX and MST/REC. ! The R/W bit decides whether the next state is within ! MST/TRX mode or within MST/REC mode. !***************************************************************************************************************************** !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : 08, A, START condition has been transmitted. ! ACTION : SLA+R/W are transmitted, ACK bit is received.! !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect .base 0108 010B 010E 8551DA 75D8C5 01A0 mts8 0x108 mov mov ajmp S1DAT,SLA ! Load SLA+R/W S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0 ! clr SI INITBASE1 1999 Aug 19 105 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 LOC OBJ SOURCE !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : STATE : 10, A repeated START condition has been transmitted. ! ACTION : SLA+R/W are transmitted, ACK bit is received.! !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect .base mts10 0x110 mov mov ajmp .sect ibase1 mov mov mov mov pop reti psw,#SELRB3 r1,#MTD r0,#MRD BACKUP,NUMBYTMST psw .base 0xa0 INITBASE1: S1DAT,SLA ! Load SLA+R/W S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0 ! clr SI INITBASE1 0110 0113 010E 8551DA 75D8C5 01A0 00A0 00A3 00A5 00A7 00AA 00AC 75D018 7930 7838 855253 D0D0 32 ! Save initial value !***************************************************************************************************************************** ! MASTER TRANSMITTER STATE SERVICE ROUTINES !***************************************************************************************************************************** !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : 18, Previous state was STATE 8 or STATE 10, SLA+W have been transmitted, ACK been received. ! ACTION : First DATA is transmitted, ACK bit is received. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -dc .sect .base 0118 011B 011D 75D018 87DA 01B5 mts18 0x118 mov mov ajmp psw,#SELRB3 S1DAT,@r1 CON !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : 20, SLA+W have been transmitted, NOT ACK has been received ! ACTION : Transmit STOP condition.! !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect .base 0120 0123 0125 75D8D5 D0D0 32 mts20 0x120 mov pop reti S1CON,#ENS1_NOTSTA_STO_NOTSI_AA_CR0 ! set STO, clr SI psw 1999 Aug 19 106 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller LOC OBJ SOURCE P8xC591 !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : 28, DATA of S1DAT have been transmitted, ACK received. ! ACTION : If Transmitted DATA is last DATA then transmit a STOP condition, else transmit next DATA. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect .base 0128 012B 012E D55285 75D8D5 01B9 mts28 0x128 djnz mov ajmp .sect mts28sb .base 0x0b0 NOTLDAT1: mov mov CON: mov inc pop reti !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : 30, DATA of S1DAT have been transmitted, NOT ACK received. ! ACTION : Transmit a STOP condition. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect .base 0130 0133 0135 75D8D5 D0D0 32 mts30 0x130 mov pop reti! !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : 38, Arbitration lost in SLA+W or DATA. ! ACTION : Bus is released, not addressed SLV mode is entered. A new START condition is ! transmitted when the IIC bus is free again.! !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect .base 0138 013B 013E 75D8E5 855352 01B9 mts38 0x138 mov mov ajmp S1CON,#ENS1_STA_NOTSTO_NOTSI_AA_CR0 NUMBYTMST,BACKUP RETmt S1CON,#ENS1_NOTSTA_STO_NOTSI_AA_CR0 ! set STO, clr SI psw NUMBYTMST,NOTLDAT1 ! JMP if NOT last DATA S1CON,#ENS1_NOTSTA_STO_NOTSI_AA_CR0 ! clr SI, set AA RETmt 00B0 00B3 00B5 00B8 00B9 00BB 75D018 87DA 75D8C5 09 D0D0 32 psw,#SELRB3 S1DAT,@r1 S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0 ! clr SI, set AA r1 psw RETmt : !***************************************************************************************************************************** ! MASTER RECEIVER STATE SERVICE ROUTINES !***************************************************************************************************************************** !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : 40, Previous state was STATE 08 or STATE 10, SLA+R have been transmitted, ACK received. ! ACTION : DATA will be received, ACK returned. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect .base 0140 0143 75D8C5 D0D0 32 mts40 0x140 mov pop reti S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0 ! clr STA, STO, SI set AA psw 1999 Aug 19 107 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 LOC OBJ SOURCE !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : 48, SLA+R have been transmitted, NOT ACK received. ! ACTION : STOP condition will be generated. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect .base STOP: mts48 0x148 mov pop reti S1CON,#ENS1_NOTSTA_STO_NOTSI_AA_CR0 ! set STO, clr SI psw 0148 014B 014D 75D8D5 D0D0 32 !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : 50, DATA have been received, ACK returned. ! ACTION : Read DATA of S1DAT. DATA will be received, if it is last DATA then NOT ACK will be returned ! else ACK will be returned. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect .base 0150 0153 0155 75D018 A6DA 01C0 .sect .base 00C0 00C3 00C6 00C8 00CB 00CC 00CE D55205 75D8C1 8003 75D8C5 08 D0D0 32 REC1: mrs50s 0xc0 djnz mov sjmp mov inc pop reti NUMBYTMST,NOTLDAT2 S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_NOTAA_CR0 ! clr SI,AA RETmr S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0 ! clr SI, set AA RETmr: r0 psw mrs50 0x150 mov mov ajmp psw,#SELRB3 @r0,S1DAT REC1 ! Read received DATA NOTLDAT2: !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : 58, DATA have been received, NOT ACK returned. ! ACTION : Read DATA of MASTER STATE SERVICE ROUTINESS1DAT and generate a STOP condition. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect .base 0158 015B 015D 75D018 A6DA 80E9 mrs58 0x158 mov mov sjmp psw,#SELRB3 @R0,S1DAT STOP 1999 Aug 19 108 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 LOC OBJ SOURCE !***************************************************************************************************************************** ! SLAVE RECEIVER STATE SERVICE ROUTINES !***************************************************************************************************************************** !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : 60, Own SLA+W have been received, ACK returned. ! ACTION : DATA will be recMASTER STATE SERVICE ROUTINESeived and ACK returned. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect .base srs60 0x160 mov mov ajmp .sect .base insrd 0xd0 mov mov pop reti r0,#SRD r1,#8 psw S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0 ! clr SI, set AA psw,#SELRB3 INITSRD 0160 0163 0166 75D8C5 75D018 01D0 00D0 00D2 00D4 00D6 7840 7908 D0D0 32 INITSRD: !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : 68, Arbitration lost in SLA and R/W as MST Own SLA+W have been received, ACK returned ! ACTION : DATA will be received and ACK returned. STA is set to restart MST mode after the bus is free again. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect .base 0168 016B 016E 75D8E5 75D018 01D0 srs68 0x168 mov mov ajmp S1CON,#ENS1_STA_NOTSTO_NOTSI_AA_CR0 psw,#SELRB3 INITSRD !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : 70, General call has been received, ACK returned. ! ACTION : DATA will be received and ACK returned. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect .base 0170 0173 0176 75D8C5 75D018 01D0 srs70 0x170 mov mov ajmp S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0 ! clr SI, set AA psw,#SELRB3 ! Initialize SRD counter initsrd !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : 78, Arbitration lost in SLA+R/W as MST. General call has been received, ACK returned. ! ACTION : DATA will be received and ACK returned. STA is set to restart MST mode after the bus is free again. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect .base 0178 017B 017E 75D8E5 75D018 01D0 srs78 0x178 mov mov ajmp S1CON,#ENS1_STA_NOTSTO_NOTSI_AA_CR0 psw,#SELRB3 ! Initialize SRD counter INITSRD 1999 Aug 19 109 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 LOC OBJ SOURCE !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : 80, Previously addressed with own SLA. DATA received, ACK returned. ! ACTION : Read DATA. ! IF received DATA was the last ! THEN superfluous DATA will be received and NOT ACK returned ! ELSE next DATA will be received and ACK returned.! !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect .base srs80 0x180 mov mov ajmp .sect .base srs80s 0xd8 djnz mov pop reti NOTLDAT3: mov inc pop reti r1,NOTLDAT3 S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_NOTAA_CR0 ! clr SI,AA psw S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0 ! clr SI, set AA r0 psw psw,#SELRB3 @r0,S1DAT REC2 ! Read received DATA 0180 0183 0185 75D018 A6DA 01D8 00D8 00DA 00DD 00DF 00E0 00E3 00E4 00E6 D906 75D8C1 D0D0 32 75D8C5 08 D0D0 32 REC2: LDAT: RETsr: !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : 88, Previously addressed with own SLA. DATA received NOT ACK returned. ! ACTION : No save of DATA, Enter NOT addressed SLV mode. ! Recognition of own SLA. General call recognized, if S1ADR. 01.! !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect .base 0188 018B 75D8C5 01E4 srs88 0x188 mov ajmp S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0 ! clr SI, set AA RETsr !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : 90, Previously addressed with general call. DATA has been received, ACK has been returned. ! ACTION : Read DATA. ! After General call only one byte will be received with ACK the second DATA ! will be received with NOT ACK. ! DATA will be received and NOT ACK returned. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect .base 0190 0193 0195 76D018 A6DA 01DA srs90 0x190 mov mov ajmp psw,#SELRB3 @r0,S1DAT LDAT ! Read received DATA 1999 Aug 19 110 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 LOC OBJ SOURCE !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : 98, Previously addressed with general call. ! DATA has been received, NOT ACK has been returned. ! ACTION : No save of DATA, Enter NOT addressed SLV mode. ! Recognition of own SLA. General call recognized, if S1ADR. 01.! !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect .base srs98 0x198 mov pop reti S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0 ! clr SI, set AA psw 0198 019B 019D 75D8C5 D0D0 32 !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : A0, A STOP condition or repeated START has been received, while still addressed as ! SLV/REC or SLV/TRX. ! ACTION : No save of DATA, Enter NOT addressed SLV mode. ! Recognition of own SLA. General call recognized, if S1ADR. 01. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect .base 01A0 01A3 01A5 75D8C5 D0D0 32 srsA0 0x1a0 mov pop reti S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0 ! clr SI, set AA psw !***************************************************************************************************************************** ! SLAVE TRANSMITTER STATE SERVICE ROUTINES !***************************************************************************************************************************** !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : A8, Own SLA+R received, ACK returned. ! ACTION : DATA will be transmitted, A bit received. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect .base 01A8 01AB 01AE 8548DA 75D8C5 01E8 .sect .base 00E8 00EB 00ED 00EE 00F0 75D018 7948 09 D0D0 32 ibase2 0xe8 mov mov inc pop reti psw,#SELRB3 r1, #STD r1 psw stsa8 0x1a8 mov mov ajmp S1DAT,STD ! load DATA in S1DAT S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0 ! clr SI, set AA INITBASE2 INITBASE2: 1999 Aug 19 111 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller LOC OBJ SOURCE P8xC591 !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : B0, Arbitration lost in SLA and R/W as MST. Own SLA+R received, ACK returned. ! ACTION : DATA will be transmitted, A bit received. ! STA is set to restart MST mode after the bus is free again. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect .base 01B0 01B3 01B6 8548DA 75D8E5 01E8 sstsb0 0x1b0 mov mov ajmp S1DAT,STD ! load DATA in S1DAT S1CON,#ENS1_STA_NOTSTO_NOTSI_AA_CR0 INITBASE2 !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : B8, DATA has been transmitted, ACK received. ! ACTION : DATA will be transmitted, ACK bit is received. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect .base 01B8 01BB 01BD 75D018 87DA 01F8 .sect .base 00F8 00FB 00FC 00FE 75D8C5 09 D0D0 32 SCON: scn 0xf8 mov inc pop reti S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0 ! clr SI, set AA r1 psw stsb8 0x1b8 mov mov ajmp psw,#SELRB3 S1DAT,@r1 SCON !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : C0, DATA has been transmitted, NOT ACK received. ! ACTION : Enter not addressed SLV mode. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect .base 01C0 01C3 01C5 75D8C5 D0D0 32 stsc0 0x1c0 mov pop reti S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0 ! clr SI, set AA psw !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : C8, Last DATA has been transmitted (AA=0), ACK received. ! ACTION : Enter not addressed SLV mode !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect .base 01C8 01CB 01CD 75D8C5 D0D0 32 stsc8 0x1c8 mov pop reti S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0 ! clr SI, set AA psw !***************************************************************************************************************************** ! END OF SI01 INTERRUPT ROUTINE !***************************************************************************************************************************** 1999 Aug 19 112 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 16 TIMER 2 16.1 Features of Timer 2 P8xC591 signal or by a rising edge on the input signal RT2, if enabled. RT2 is enabled by setting bit T2ER (TM2CON.5). When the least significant byte of the timer overflows or when a 16-bit overflow occurs, an interrupt request may be generated. Either or both of these overflows can be programmed to request an interrupt. In both cases, the interrupt vector will be the same. When the lower byte (TML2) overflows, flag T2B0 (TM2CON) is set and flag T20V (TM2lR) is set when TMH2 overflows. These flags are set one cycle after an overflow occurs. Note that when T20V is set, T2B0 will also be set. To enable the byte overflow interrupt, bits ET2 (lEN1.7, enable overflow interrupt, see Table 67) and T2lS0 (TM2CON.6, byte overflow interrupt select) must be set. Bit TWBO (TM2CON.4) is the Timer T2 byte overflow flag. To enable the 16-bit overflow interrupt, bits ET2 (lE1.7, enable overflow interrupt) and T2lS1 (TM2CON.7, 16-bit overflow interrupt select) must be set. Bit T2OV (TM2lR.7) is the Timer T2 16-bit overflow flag. All interrupt flags must be reset by software. To enable both byte and 16-bit overflow, T2lS0 and T2lS1 must be set and two interrupt service routines are required. A test on the overflow flags indicates which routine must be executed. For each routine, only the corresponding overflow flag must be cleared. Timer T2 may be reset by a rising edge on RT2 (P3.1) if the Timer T2 external reset enable bit (T2ER) in TM2CON is set. This reset also clears the prescaler. In the Idle mode, the timer/counter and prescaler are reset and halted. Timer T2 is controlled by the TM2CON special function register (see Section 16.1.1). Timer T2 is a 16-bit timer consisting of two registers TMH2 (HIGH byte) and TML2 (LOW byte). The 16-bit timer/counter can be switched off or clocked via a prescaler from one of two sources: fCLK/6 or an external signal. When Timer T2 is configured as a counter, the prescaler is clocked by an external signal on T2 (P3.O). A rising edge on T2 increments the prescaler, and the maximum repetition rate is one count per machine cycle (1 MHz with a 6 MHz oscillator). The maximum repetition rate for Timer T2 is twice the maximum repetition rate for Timer 0 and Timer 1. T2 (P3.0) is sampled at S2P1 and again at S5P1 (i.e., twice per machine cycle). A rising edge is detected when T2 is LOW during one sample and HIGH during the next sample. To ensure that a rising edge is detected, the input signal must be LOW for at least 12 cycle and then HIGH for at least 12 cycle. If a rising edge is detected before the end of S2P1, the timer will be incremented during the following cycle; otherwise it will be incremented one cycle later. The prescaler has a programmable division factor of 1, 2, 4, or 8 and is cleared if its division factor or input source is changed, or if the timer/counter is reset. Timer T2 may be read "on the fly" but possesses no extra read latches, and software precautions may have to be taken to avoid misinterpretation in the event of an overflow from least to most significant byte while Timer T2 is being read. Timer T2 is not loadable and is reset by the RST Table 66 Timer T2 Interrupt Enable Register IEN1 (address E8H) 7 ET2 6 ECAN 5 ECM1 4 ECM0 3 ECT3 2 ECT2 1 ECT1 0 ECT0 Table 67 Description of interrupt Enable Register IEN1 bits BIT 7 6 5 4 3 2 1 0 SYMBOL ET2 ECAN ECM1 ECM0 ECT3 ECT2 ECT1 ECT0 Enable CAN interrupt. Enable T2 Comparator 1 interrupt. Enable T2 Comparator 0 interrupt. Enable T2 Capture register 3 interrupt. Enable T2 Capture register 2 interrupt. Enable T2 Capture register 1 interrupt. Enable T2 Capture register 0 interrupt. FUNCTION Enable Timer T2 overflow interrupt(s). 1999 Aug 19 113 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 16.1.1 T2 CONTROL REGISTER (TM2CON) P8xC591 Table 68 T2 Control Register (address EAH) 7 T2IS1 6 T2IS0 5 T2ER 4 T2BO 3 T2P1 2 T2P0 1 T2MS1 0 T2MS0 Table 69 Description of TM2CON bits BIT 7 6 5 4 3 2 1 0 SYMBOL T2IS1 T2IS0 T2ER T2BO T2P1 T2P0 T2MS1 T2MS0 Timer T2 mode select (see Table 71). DESCRIPTION Timer T2 16-bit overflow interrupt select. Timer T2 byte overflow interrupt select. Timer T2 external reset enable. When this bit is set, Timer T2 may be reset by a rising edge on RT2 (P3.1). Timer T2 byte overflow interrupt flag. Timer T2 prescaler select (see Table 70). Table 70 Timer 2 prescaler select T2P1 0 0 1 1 T2P0 0 1 0 1 clock source 1 2 1 4 1 8 TIMER T2 CLOCK x clock source x clock source x clock source Table 71 Timer 2 mode select T2MS1 0 0 1 1 T2MS0 0 1 0 1 Timer T2 halted (off) 1 12 MODE SELECTED x fCLK T2 clock source Test mode; do not use T2 clock source = pin T2 1999 Aug 19 114 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 16.1.2 TIMER T2 EXTENSION 16.1.3 P8xC591 TIMER T2, CAPTURE AND COMPARE LOGIC When a 6 MHz oscillator is used, a 16-bit overflow on Timer T2 occurs every 65.5, 131, 262, or 524 ms, depending on the prescaler division ratio; i.e., the maximum cycle time is approximately 0.5 seconds. In applications where cycle times are greater than 0.5 seconds, it is necessary to extend Timer T2. This is achieved by selecting fCLK/6 as the clock source (set T2MS0, reset T2MS1), setting the prescaler division ration to 18 (set T2P0, set T2P1), disabling the byte overflow interrupt (reset T2lS0) and enabling the 16-bit overflow interrupt (set T2lS1). The following software routine is written for a three-byte extension which gives a maximum cycle time of approximately 2400 hours. Timer T2 is connected to four 16-bit capture registers and three 16-bit compare registers. A capture register may be used to capture the contents of Timer T2 when a transition occurs on its corresponding input pin. A compare register may be used to set or reset port 3 output pins at certain pre-programmable time intervals. The combination of Timer T2 and the capture and compare logic is very powerful in applications involving rotating machinery, automotive injection systems, etc. Timer T2 and the capture and compare logic are shown in Figure 45. OVINT: PUSH ACO ; save accumulator PUSH PSW ; save status INC TlMEX1 ; increment first byte (low order) of extended timer MOV A,TlMEX1 JNZ INTEX ; jump to INTEX if; there is no overflow INC TlMEX2 ; increment second byte MOV A,TlMEX2 JNZ INTEX ; jump to INTEX if there is no overflow INC TlMEX3 ; increment third byte (high order) INTEX: CLR T2OV POP PSW POP ACC RETI ; reset interrupt flag ; restore status ; restore accumulator ; return from interrupt 1999 Aug 19 115 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 handbook, full pagewidth CT0I/INT2 INT(1) CTI0 CT0 CT1I/INT3 INT(1) CTI1 CT1 CT2I/INT4 INT(1) CTI2 CT2 CT3I/INT5 INT(1) CTI3 CT3 off fclk T2 RT2 T2ER external reset enable COMP S S S S R R R R P3.2 P3.3 P3.4 I/O port 3 P3.5 CM0 (S) CM1 (R) CM2 MHI046 8-bit overflow interrupt 1/6 PRESCALER T2 COUNTER 16-bit overflow interrupt INT(1) COMP INT(1) COMP * * * * STE * * * * RTE T2 SFR address: TML2 = lower 8 bits TMH2 = higher 8 bits S = set R = reset * = reserved (1) to internal logic Fig.45 Block diagram of Timer 2. 1999 Aug 19 116 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 16.1.4 CAPTURE LOGIC P8xC591 The four 16-bit capture registers that Timer T2 is connected to are: CT0, CT1, CT2, and CT3. These registers are loaded with the contents of Timer T2, and an interrupt is requested upon receipt of the input signals CT0l, CT1I, CT2l, or CT3l. These input signals are shared with port 1. The four interrupt flags are in the Timer T2 interrupt register (TM2lR special function register). If the capture facility is not required, these inputs can be regarded as additional external interrupt inputs (INT2 to INT5). Using the capture control register CTCON (see Section 16.1.4.1), these inputs may capture on a rising edge, a falling edge, or on either a rising or falling edge. The inputs are sampled during S1P1 of each cycle. When a selected edge is detected, the contents of Timer T2 are captured at the end of the cycle. 16.1.4.1 Capture Control Register (CTCON) Table 72 Capture Control Register (address EBH) 7 CTN3 6 CTP3 5 CTN2 4 CTP2 3 CTN1 2 CTP1 1 CTN0 0 CTP0 Table 73 Description of CTCON bits BIT 7 6 5 4 3 2 1 0 16.1.5 SYMBOL CTN3 CTP3 CTN2 CTP2 CTN1 CTP1 CTN0 CTP0 DESCRIPTION Capture Register 3 triggered by a falling edge on CT3l. Capture Register 3 triggered by a rising edge on CT3l. Capture Register 2 triggered by a falling edge on CT2l. Capture Register 2 triggered by a rising edge on CT2l. Capture Register 1 triggered by a falling edge on CT1l. Capture Register 1 triggered by a rising edge on CT1l. Capture Register 0 triggered by a falling edge on CT0l. Capture Register 0 triggered by a rising edge on CT0l. CM0 occurs, the controller sets bits 0-3 of port 3 if the corresponding bits of the set enable register STE are at logic 1 (see Section 16.1.6.2). When a match with CM1 occurs, the controller resets bits 0-3 of port 3 if the corresponding bits of the reset/enable register RTE are at logic 1 (see Section 16.1.6.1). If RTE is "0", then P3.n is not affected by a match between CM1 or CM2 and Timer 2. Thus, if the current operation is "set," the next operation will be "reset" even if the port latch is reset by software before the "reset" operation occurs. CM0, CM1, and CM2 are reset by the RST signal. The modified port latch information appears at the port pin during S5P1 of the cycle following the cycle in which a match occurred. If the port is modified by software, the outputs change during S1P1 of the following cycle. Each port 3 bit (0-3) can be set or reset by software at any time. A hardware modification resulting from a comparator match takes precedence over a software modification in the same cycle. When the comparator results require a "set" and a "reset" at the same time, the port latch will be reset. 117 MEASURING TIME INTERVALS USING REGISTERS When a recurring external event is represented in the form of rising or falling edges on one of the four capture pins, the time between two events can be measured using Timer T2 and a capture register. When an event occurs, the contents of Timer T2 are copied into the relevant capture register and an interrupt request is generated. The interrupt service routine may then compute the interval time if it knows the previous contents of Timer T2 when the last event occurred. With a 6 MHz oscillator, Timer T2 can be programmed to overflow every 524 ms. When event interval times are shorter than this, computing the interval time is simple, and the interrupt service routine is short. For longer interval times, the Timer T2 extension routine may be used. 16.1.6 COMPARE LOGIC Each time Timer T2 is incremented, the contents of the three 16-bit compare registers CM0, CM1, and CM2 are compared with the new counter value of Timer T2. When a match is found, the corresponding interrupt flag in TM2lR is set at the end of the following cycle. When a match with 1999 Aug 19 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 16.1.6.1 Reset/Toggle Enable Register (RTE) P8xC591 Table 74 Reset/Toggle enable register (address EFH) 7 - 6 - 5 - 4 - 3 RP35 2 RP34 1 RP33 0 RP32 Table 75 Description of RTE bits BIT 7 to 4 3 2 1 0 SYMBOL - RP35 RP34 RP33 RP32 Reserved. If HIGH then P3.5 is reset on a match between CM2 and T2. If HIGH then P3.4 is reset on a match between CM2 and T2. If HIGH then P3.3 is reset on a match between CM2 and T2. If HIGH then P3.2 is reset on a match between CM2 and T2. DESCRIPTION 16.1.6.2 Set Enable Register (STE) Table 76 Set enable register (address EEH) 7 - 6 - 5 - 4 - 3 SP35 2 SP34 1 SP33 0 SP32 Table 77 Description of STE bits BIT 7 3 2 1 0 SYMBOL - SP35 SP34 SP33 SP32 Reserved. If HIGH then P3.5 is set on a match between CM2 and T2. If HIGH then P3.4 is set on a match between CM2 and T2. If HIGH then P3.3 is set on a match between CM2 and T2. If HIGH then P3.2 is set on a match between CM2 and T2. DESCRIPTION 1999 Aug 19 118 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 16.1.7 TIMER T2 INTERRUPT FLAG REGISTER TM2IR P8xC591 Seven of the eight Timer T2 interrupt flags are located in special function register TM2lR (see Section 16.1.7.1). The eights flag is TM2CON.4. The CT0l and CT1I flags are set during S4 of the cycle in which the contents of Timer T2 are captured. CT0l is scanned by the interrupt logic during S2, and CT1I is scanned during S3. CT2l and CT3l are set during S6 and are scanned during S4 and S5. The associated interrupt requests are recognized during the following cycle. If these flags are polled, a transition at CT0l or CT1I will be recognized one cycle before a transition on CT2l or CT3l since registers are read during S5. The CMI0, CMl1 and CMl2 flags are set during S6 of the cycle following a match. CMl0 is scanned by the interrupt logic during S2; CMl1 and CMl2 are scanned during S3 and S4. A match of CMl0 and CMl1 will be recognized by the interrupt logic (or by polling the flags) two cycles after the match takes place. A match of CMl2 will cause no interrupt, this flag can be polled only. The 16-bit overflow flag (T2OV) and the byte overflow flag (T2BO) are set during S6 of the cycle in which the overflow occurs. These flags are recognized by the interrupt logic during the next cycle. Special function register lP1 (see Section 16.1.7.2) is used to determine the Timer T2 interrupt priority. Setting a bit high gives that function a high priority, and setting a bit low gives the function a low priority. The functions controlled by the various bits of the lP1 register are shown in Section 16.1.6.2. 16.1.7.1 Interrupt Flag Register (TM2IR) Table 78 Interrupt flag register (address C8H) 7 T2OV 6 CMI2/CAN 5 CMI1 4 CMI0 3 CTI3 2 CTI2 1 CTI1 0 CTI0 Table 79 Description of TM2IR bits BIT 7 6 5 4 3 2 1 0 SYMBOL T2OV CMI2/CAN CMI1 CMI0 CTI3 CTI2 CTI1 CTI0 DESCRIPTION T2: 16-bit overflow interrupt flag. CM2: flag (for polling only). CAN: CAN interrupt flag (polling only). CM1: interrupt flag. CM0: interrupt flag. CT3: interrupt flag. CT2: interrupt flag. CT1: interrupt flag. CT0: interrupt flag. 16.1.7.2 Interrupt Priority Register 1 (IP1) Table 80 Interrupt Priority Register 1 (address F8H) 7 PT2 6 PCAN 5 PCM1 4 PCM0 3 PCT3 2 PCT2 1 PCT1 0 PCT0 Table 81 Description of IP1 bits BIT 7 6 5 4 3 2 1 0 1999 Aug 19 SYMBOL PT2 PCAN PCM1 PCM0 PCT3 PCT2 PCT1 PCT0 DESCRIPTION T2 overflow interrupt(s) priority level. CAN interrupt priority level. T2 comparator 1 priority interrupt level. T2 comparator 0 priority interrupt level. T2 capture register 3 priority interrupt level. T2 capture register 2 priority interrupt level. T2 capture register 1 priority interrupt level. T2 capture register 0 priority interrupt level. 119 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 17 WATCHDOG TIMER (T3) In addition to Timer T2 and the standard timers, a Watchdog Timer (T3) is also incorporated on the P8xC591. The purpose of a Watchdog Timer is to reset the microcontroller if it enters erroneous processor states (possibly caused by electrical noise or RFI) within a reasonable period of time. An analogy is the "dead man's handle" in railway locomotives. When enabled, the watchdog circuitry will generate a system reset if the user program fails to reload the Watchdog Timer within a specified length of time known as the "watchdog interval". Watchdog Circuit Description: The watchdog timer (Timer T3) consists of an 8-bit timer with an 11-bit prescaler as shown in Figure 46. The prescaler is fed with a signal whose frequency is 16 the oscillator frequency (1 MHz with a 6 MHz oscillator). The 8-bit timer is incremented every "t" seconds, where: T3 is incremented every 768 s, derived from the oscillator frequency of 16 MHz by the following formula: t = 6 x 2048 x 1/fCLK = 768 s at fCLK = 16 MHz. If the 8-bit timer overflows, a short internal reset pulse is generated which will reset the P8xC591. A short output reset pulse is also generated at the RST pin. This short output pulse (3 machine cycles) may be destroyed if the RST pin is connected to a capacitor. This would not, however, affect the internal reset operation. Watchdog operation is activated by setting the `WDE' bit in Special Function Register AUXR1. Once `WDE' is set, it can only be disabled by applying a reset. How to Operate the Watchdog Timer: The watchdog timer has to be reloaded within periods that are shorter than the programmed watchdog interval; otherwise the watchdog timer will overflow and a system reset will be generated. The user program must therefore continually execute sections of code which reload the watchdog timer. The period of time elapsed between execution of these sections of code must never exceed the watchdog interval. When using a 16 MHz oscillator, the watchdog interval is programmable between 768 s and 196 ms. In order to prepare software for watchdog operation, a programmer should first determine how long his system can sustain an erroneous processor state. The result will be the maximum watchdog interval. As the maximum watchdog interval becomes shorter, it becomes more difficult for the programmer to ensure that the user program always reloads the watchdog timer within the watchdog interval, and thus it becomes more difficult to implement watchdog operation. 1999 Aug 19 P8xC591 The programmer must now partition the software in such a way that reloading of the watchdog is carried out in accordance with the above requirements. The programmer must determine in execution times of all software modules. The effect of possible conditional branches, subroutines, external and internal interrupts must all be taken into account. Since it may be very difficult to evaluate the execution times of some sections of code, the programmer should use worst case estimations. In any event, the programmer must make sure that the watchdog is not activated during normal operation. The watchdog timer is reloaded in two stages in order to prevent erroneous software from reloading the watchdog. First PCON.4 (WLE) must be set. The T3 may be loaded. When T3 is loaded, PCON.4 (WLE) is automatically reset. T3 cannot be loaded if PCON.4 (WLE) is reset. Reload code may be put in a subroutine as it is called frequently. Since Timer T3 is an up-counter, a reload value of 00H gives the maximum watchdog interval (255 ms with a 12 MHz oscillator), and a reload value of 0FFH gives the minimum watchdog interval (1 ms with a 12 MHz oscillator). In the Idle mode, the watchdog circuitry remains active. When watchdog operation is implemented, the Power-down mode cannot be used since both states are contradictory. Thus, when watchdog operation is enabled by setting `WDE' bit in AUXR1.4, it is not possible to enter the Power-down mode, and an attempt to set the Power-down bit (PCON.1) will have no effect. PCON.1 will remain at logic 0. Watchdog Software Example: The following example shows how watchdog operation might be handled in a user program. ; at the program start: EQU 0FFH ;address of watchdog timer T3 PCON EQU 087H ;address of PCON SFR WATCH-INTV EQU 156 ;watchdog interval (e.g., 2 x 100 ms) ;to be inserted at each watchdog location within ;the user program: LCALL WATCHDOG ;watchdog service routine: WATCHDOG: ORL PCON,#10H ;set condition flag (PCON.4) MOV T3,WATCH-INV ;load T3 with watchdog interval RET T3 If its possible for this subroutine to be called in an erroneous state, then the condition flag WLE should be set at different parts of the main program. 120 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 handbook, full pagewidth INTERNAL BUS 1/6 fclk PRESCALER 11-BIT CLEAR TIMER T3 (8-BIT) LOAD LOADEN to reset circuitry (1) CLEAR write T3 WLE PCON.4 PD LOADEN AUXR1.4 WDE PCON.1 INTERNAL BUS MHI047 (1) See Fig.8. Fig.46 Functional diagram of T3 Watchdog Timer. 1999 Aug 19 121 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 18 PULSE WIDTH MODULATED OUTPUTS The P8xC591 contains two Pulse Width Modulated (PWM) output channels (see Fig.47). These channels generate pulses of programmable length and interval. The repetition frequency is defined by an 8-bit prescaler PWMP, which supplies the clock for the counter. The prescaler and counter are common to both PWM channels. The 8-bit counter counts modulo 255, i.e., from 0 to 254 inclusive. The value of the 8-bit counter is compared to the contents of two registers: PWM0 and PWM1. Provided the contents of either of these registers is greater than the counter value, the corresponding PWM0 or PWM1 output is set LOW. If the contents of these registers are equal to, or less than the counter value, the output will be HIGH. The pulse-width-ratio is therefore defined by the contents of the registers PWM0 and PWM1. The pulse-width-ratio is in the range of 0255 to 255255 and may be programmed in increments of 1255. Buffered PWM outputs may be used to drive DC motors. The rotation speed of the motor would be proportional to the contents of PWMn. The PWM outputs may also be configured as a dual DAC. P8xC591 In this application, the PWM outputs must be integrated using conventional operational amplifier circuitry. If the resulting output voltages have to be accurate, external buffers with their own analog supply should be used to buffer the PWM outputs before they are integrated. The repetition frequency fPWM, at the PWMn outputs is given by: f CLK f PWM = ----------------------------------------------------( PWMP + 1 ) x 255 This gives a repetition frequency range of 246 Hz to 62.8 kHz (at fCLK = 16 MHz). By loading the PWM registers with either 00H or FFH, the PWM channels will output a constant HIGH or LOW level, respectively. Since the 8-bit counter counts modulo 255, it can never actually reach the value of the PWM registers when they are loaded with FFH. When a compare register (PWM0 or PWM1) is loaded with a new value, the associated output is updated immediately. It does not have to wait until the end of the current counter period. Both PWMn output pins are driven by push-pull drivers. These pins are not used for any other purpose. handbook, full pagewidth PWM0 8-BIT COMPARATOR INTERNAL BUS OUTPUT BUFFER PWM0 fCLK PRESCALER PWMP 8-BIT COUNTER 8-BIT COMPARATOR OUTPUT BUFFER PWM1 PWM1 MHI048 Fig.47 Functional diagram of Pulse Width Modulated outputs. 1999 Aug 19 122 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 18.1 Prescaler Frequency Control Register (PWMP) P8xC591 Reading PWMP gives the current reload value. The actual count of the prescaler cannot be read. Table 82 Prescaler Frequency Control Register (address FEH), Reset Value = 00H 7 PWMP.7 6 PWMP.6 5 PWMP.5 4 PWMP.4 3 PWMP.3 2 PWMP.2 1 PWMP.1 0 PWMP.0 Table 83 Description of PWMP bits BIT 7 to 0 18.2 SYMBOL PWMP.7 to PWMP.0 DESCRIPTION Prescaler division factor. The Prescaler division factor = (PWMP) + 1. Pulse Width Register 0 (PWM0) Table 84 Pulse width register (address FCH), Reset Value = 00H 7 PWM0.7 6 PWM0.6 5 PWM0.5 4 PWM0.4 3 PWM0.3 2 PWM0.2 1 PWM0.1 0 PWM0.0 Table 85 Description of PWM0 bits BIT 7 to 0 SYMBOL PWM0.7 to PWM0.0 Pulse width ratio. ( PWM0 ) LOW/HIGH ratio of PWM0 signals = ----------------------------------------255 - ( PWM0 ) 18.3 Pulse Width Register 1 (PWM1) DESCRIPTION Table 86 Pulse width register (address FDH) 7 PWM1.7 6 PWM1.6 5 PWM1.5 4 PWM1.4 3 PWM1.3 2 PWM1.2 1 PWM1.1 0 PWM1.0 Table 87 Description of PWM1 bits BIT 7 to 0 SYMBOL PWM1.7 to PWM1.0 Pulse width ratio. ( PWM1 ) LOW/HIGH ratio of PWM1 signals = ----------------------------------------255 - ( PWM1 ) DESCRIPTION 1999 Aug 19 123 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 19 PORT 1 OPERATION Port 1 may be used to input up to 6 analog signals ADC. Unused ADC inputs may be used to input digital inputs. These inputs have an inherent hysteresis to prevent the input logic from drawing excessive current from the power lines when driven by analog signals. Channel to channel crosstalk (Ct) should be taken into consideration when both analog and digital signals are simultaneously input to Port 3 (see Chapter 24 "DC Characteristics"). 20 ANALOG-TO-DIGITAL CONVERTER (ADC) 20.1 ADC features 20.2 ADC functional description P8xC591 * 10-bit resolution * 6 multiplexed analog inputs * Start of a conversion by software or with an external signal * Conversion time for one analog-to-digital conversion: 18.75 s @ 16 MHz * Differential non-linearity (DLe): 1 LSB * Integral non-linearity (ILe): 2 LSB * Offset error (OSe): 2 LSB * Gain error (Ge): 4% * Absolute voltage error (Ae): 3 LSB * Channel-to-channel matching (Mctc): 1 LSB * Crosstalk between analog inputs (Ct): < 60 dB at 100 kHz * Monotonic and no missing codes * Separated analog (VSSA) and digital (VDD, VSS) supply voltages * Reference voltage special pin: Vref(p)(A). For information on the ADC characteristics, refer to Chapter 24. The analog input circuitry consists of an 6-input analog multiplexer and a 10-bit, straight binary, successive approximation ADC. The A/D can also be operated in 8-bit mode with faster conversion times by setting bit ADC8 (AUXR1.7). The 8-bit result will be contained in the ADCH register. The analog reference voltage and analog power supplies are connected via separate input pins. For 10-bit accuracy, the conversion takes 50 machine cycles, i.e., 18.75 s at an oscillator frequency of 16 MHz. For the 8-bit mode, the conversion takes 24 machine cycles. Input voltage swing is from 0 V to +5 V. Because the internal DAC employs a ratiometric potentiometer, there are no discontinouties in the converter characteristic. Figure 48 shows a functional diagram of the analog input circuitry. The ADC has the option of either being powered off in Idle mode for reduced power consumption or being active in the Idle mode for reducing internal noise during the conversion. This option is selected by the AIDL bit of AUXR1 register (AUXR1.6). With the AIDL bit set, the ADC is active in the Idle mode, and with the AIDL bit cleared, the ADC is powered off in Idle mode. 1999 Aug 19 124 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 handbook, full pagewidth ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 n.c. n.c. + ANALOG INPUT MULTIPLEXER ANALOG REF. 10-BIT A/D CONVERTER ANALOG GROUND ADCON 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ADCH INTERNAL BUS MHI050 Fig.48 Functional diagram of Analog Input Circuitry. 20.3 10-Bit Analog-to-Digital Conversion Figure 48 shows the elements of a successive approximation (SA) ADC. The ADC contains a DAC which converts of a successive approximation register to a voltage (VDAC) which is compared to the analog input voltage (VIN). The output of the comparator is fed to the successive approximation control logic which controls the successive approximation register. A conversion is initiated by setting ADCS in ADCON register. ADCS can bet set by software only. The software start mode is selected when control bit ADCON.5 (ADEX) = 0. A conversion is then started by setting control bit ADCON.3 (ADCS). The software start mode is selected when ADCON.5 = 1, and a conversion may be started by setting ADCON.3. When a conversion is initiated, the conversion starts at the beginning of the machine cycle which follows the instruction that sets ADCS. ADCS is actually implemented with two flip-flops; a command flip-flop which is affected by set operations, and a status flag which is accessed during read operations. The next two machine cycles are used to initiate the converter. At the end of the first cycle, the ADCS status flag is set and a value of "1" will be returned if the ADCS flag is read while the conversion is progress. Sampling of the analog input commences at the end of the second cycle. During the next eight machine cycles, the voltage at the previously selected pin of port 1 is sampled, and this input voltage should be stable in order to obtain a useful sample. In any event, the input voltage slew rate must be less than 10 V/ms in order to prevent an undefined result. The successive approximation control logic first sets the most significant bit and clears all other bits in the successive approximation register (10 0000 0000B). The output of the DAC (50% full scale) is compared to the input voltage VIN. If the input voltage is greater than VDAC, then the bit remains set; otherwise it is cleared. The successive approximation control logic now sets the next most significant bit (11 0000 0000B or 01 0000 0000B, depending on the previous result), and VDAC is compared to VIN again. If the input voltage is greater than VDAC, then the bit being tested remains set; 125 1999 Aug 19 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller otherwise the bit being tested is cleared. This process is repeated until all ten bits have been tested, at which stage the result of the conversion is held in the successive approximation register. Figure 48 shows a conversion flow chart. The bit pointer identifies the bit under test. The conversion takes four machine cycles per bit. The end of the 10-bit conversion is flagged by control bit ADCON.4 (ADCI). The upper 8 bits of the result are held in Special Function Register ADCH, and the two remaining bits are held in ADCON.7 (ADC.1) and ADCON.6 (ADC.0). The user may ignore the two least significant bits in ADCON and use the ADC as an 8-bit converter (8 upper bits in ADCH). In any event, the total actual conversion P8xC591 time is 50 machine cycles for the P8xC591. ADCI will be set and the ADCS status flag will be reset 50 (or 24) cycles after the command flip-flop (ADCS) is set. Control bits ADCON.0, ADCON.1, and ADCON.2 are used to control an analog multiplexer which selects one of six analog channels (see Section 20.3.1). An ADC conversion in progress is unaffected by a new software ADC start. The result of a completed conversion remains unaffected provided ADCI = logic 1; a new ADC conversion already in progress is aborted when the Idle or Power-down mode is entered. The result of a completed conversion (ADCI = logic 1) remains unaffected when entering the Idle mode. handbook, full pagewidth Vin VDAC SUCCESSIVE APPROXIMATION REGISTER SUCCESSIVE APPROXIMATION CONTROL LOGIC DAC VDAC full scale 1 Vin 3/4 START STOP 15/16 7/8 29/32 59/64 1/2 0 1 2 3 4 5 t/tau 6 MHI051 Fig.49 Successive Approximation ADC. 1999 Aug 19 126 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 handbook, full pagewidth SOC Start of conversion RESET SAR [BIT POINTER] = MSB [BIT] N = 1 CONVERSION TIME 1 TEST COMPLETE 0 [BIT] N = 0 [BIT POINTER] + 1 TEST BIT POINTER END END MHI052 EOC End of conversion Fig.50 A/D Conversion Flowchart. 1999 Aug 19 127 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 20.3.1 ADC CONTROL REGISTER (ADCON) P8xC591 Table 88 ADC Control Register (address C5H); Reset value = xx00 0000B 7 ADC.1 6 ADC.0 5 ADEX 4 ADCI 3 ADCS 2 AADR2 1 AADR1 0 AADR0 Table 89 Description of ADCON bits BIT 7 6 5 4 SYMBOL ADC.1 ADC.0 - ADCI Bit 1 of ADC result. Bit 0 of ADC result. Reserved for future use. ADC interrupt flag. This flag is set when an A/D conversion result is ready to be read. An interrupt is invoked if its is enabled. The flag may be cleared by the interrupt service routine. While this flag is set, the ADC cannot start a new conversion. ADCI cannot be set by software. ADC start and status. Setting this bit starts an A/D conversion. It is set by software. The ADC logic ensures that this signal is HIGH while the ADC is busy. On completion of the conversion. ADCS is reset immediately after the interrupt flag has been set. ADCS cannot be reset by software. A new conversion may not be started while either ADCS or ADCI is high (see Table 90). If ADDCI is cleared by software while ADCS is set at the same time, a new A/D conversion with the same channel number may be started. But it is recommended to reset ADCI before ADCS is set. 2 to 0 AADR2 to AADR0 Analogue input select: This binary coded address selects one of the six analogue port bits of P1 to be input to the converter. It can only be changed when ADCI and ADCS are both LOW. DESCRIPTION 3 ADCS Table 90 ADC status ADCI 0 0 1 1 ADCS 0 1 0 1 ADC STATUS ADC not busy; a conversion can be started ADC busy; start of a new conversion is blocked Conversion completed; start of a new conversion requires ADCI=0 Conversion completed; start of a new conversion requires ADCI=0 Table 91 Selected analog channel AADR2 0 0 0 0 1 1 AADR1 0 0 1 1 0 0 AADR0 0 1 0 1 0 1 SELECTED ANALOG CHANNEL ADC0 (P1.2) ADC1 (P1.3) ADC2 (P1.4) ADC3 (P1.5) ADC4 (P1.6) ADC5 (P1.7) 1999 Aug 19 128 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 20.4 10-Bit ADC Resolution and Analog Supply 20.5 Power Reduction Modes P8xC591 Figure 48 shows how the ADC is realized. The ADC has its own analog ground (AVSS) and a positive analog reference pin (Vref+) connected to each end of the DAC's resistance-ladder. The ladder has 1023 equally spaced taps, separated by a resistance of "R". The first tap is located 0.5 x R above AVSS, and the last tap is located 1.5 x R below Vref+. This gives a total ladder resistance of 1024 x R. This structure ensures that the DAC is monotonic and results in a symmetrical quantization error is shown in Figure 48. For input voltages between 0 V and + 1/2 LSB, the 10-bit result of an A/D conversion will be 00 0000 0000B = 0000H. For input voltages between (Vref+) - 3/2 LSB and Vref+, the result of a conversion will be 11 1111 1111B = 3FFFH. AVref+ may be between VDD +0.2 V and AVSS 0.2 V. AVref+ should be positive 0 V and AVref+. If the analog input voltage range is from 2 V to 4 V, the 10-bit resolution can be obtained over this range if AVref+ = 4 V. The result can always can always be calculated from the following formula: V IN Result = 1024 x --------------AV ref+ The P8xC591 has two reduced power modes of operation: the Idle mode and the Power-down mode. These modes are entered by setting bits in the PCON Special Function Register. When the P8xC591 enters the Idle mode, the following functions are disabled: CPU Timer T2 PWM0, PWM1 ADC (halted) (halted and reset) (reset; outputs are high) (may be enabled for operation in Idle mode by setting bit AIDC (AUXR1.6). In Idle mode, the following functions remain active: Timer 0 Timer 1 Timer T3 SIO0 SIO1 External interrupts When the P8xC591 enters the Power-down mode, the oscillator is stopped. The Power-down mode is entered by setting the PD bit in the PCON register. The PD bit can only be set if the `WDE' bit is 0. handbook, full pagewidth AVref+ R/2 R R 1023 1022 1021 MSB START Total resistance = 1023R + 2 x R/ = 1024R 3 2 R R R/2 AVSS Vref Vin Value 0000 0000 00 Value 1111 1111 11 0 DECODER SUCCESSIVE APPROXIMATION REGISTER SUCCESSIVE APPROXIMATION CONTROL LOGIC READY 1 LSB MHI053 COMPARATOR is output for voltages 0 V + 12 LSB is output for voltages (Vref+ 32 LSB) to Vref+ Fig.51 ADC Realization. 1999 Aug 19 129 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 handbook, full pagewidth IN + 1 IN SmN + 1 SmN RmN + 1 RmN to comparator + Rs VANALOG input Cs MULTIPLEXER Cc MHI054 Rm = 0.5 - 3 k CS + CC = 15 pF maximum RS = Recommended < 9.6 k for 1 LSB @ 12 MHz Note: Because the analog to digital converter has a sampled-data comparator, the input looks capacitive to a source. When a conversion is initiated, switch Sm closes for 8 tCY (4 s @ 12 MHz crystal frequency) during which time capacitance CS + CC is changed. It should be noted that the sampling causes the analog input to prevent a varying load to an analog source. Fig.52 A/D Input: Equivalent Circuit. handbook, full pagewidth 101 CODE OUT 100 011 010 001 000 0 q 2q 3q 4q 5q Vin QUANTIZATION ERROR q = LSB = 5 mV Vin - Vdigital +q/2 Vin -q/2 MHI055 SYMMETRICAL QUANTIZATION ERROR Fig.53 Effective Conversion Characteristic. 1999 Aug 19 130 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 21 INTERRUPTS The 8xC591 has fifteen interrupt sources, each of which can be assigned one of four priority levels. The five interrupt sources common to the 80C51 are the external interrupts (INT0 and INT1), the timer 0 and timer 1 interrupts (lT0 and IT1), and the serial I/O interrupt (RI or TI). In the 8xC591, the standard serial interrupt is called SIO0. The seven Timer T2 interrupts are generated by flags CTl0-CTI3, CMl0-CMl1, and by the logical OR of flags T2OV and T2BO. Flags CTl0 to CTI3 are set by input signals CT0l to CT3I. The inputs INT2 to INT5 can be regarded as 4 additional external interrupts, if the capture facility of Timer T2 is not used (details see Timer T2 in Section 16.1.4.1). Flags CMl0 to CMl1 are set when a match occurs between Timer T2 and the compare registers CM0 and CM1. When an 8-bit or 16-bit overflow occurs, flags T2BO and T2OV are set, respectively. These eight flags are not cleared by hardware and must be reset by software to avoid recurring interrupts. The ADC interrupt is generated by the ADCl flag in the ADC control register (ADCON). This flag is set when an ADC conversion result is ready to be read. ADCl is not cleared by hardware and must be reset by software to avoid recurring interrupts. The SIO1 (I2C) interrupt is generated by the SI flag in the SI01 control register (S1CON). This flag is set when S1STA is loaded with a valid status code. The ADCl flag may be reset by software. It cannot be set by software. All other flags that generate interrupts may be set or cleared by software, and the effect is the same as setting or resetting the flags by hardware. Thus, interrupts may be generated by software and pending interrupts can be cancelled by software. A CAN interrupt is generated (vector address 006BH) when one or more bits of CANCON register are set (refer to CAN Section 12.5.5 Interrupt Register (IR) for details). 21.1 Interrupt Enable Registers P8xC591 Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable Special Function Registers lENO and lEN1. All interrupt sources can also be globally enabled or disabled by setting or clearing bit EA in lENO. The interrupt enable registers are described in Section 21.2.1 and 21.2.2). There are 3 SFRs associated with each of the four-level interrupts. They are the lENx, lPx, and lPxH (see Section 21.2.3 to 21.2.6). The lPxH (Interrupt Priority High) register makes the four-level interrupt structure possible. The function of the lPxH SFR is simple and when combined with the lPx SFR determines the priority of each interrupt. The priority of each interrupt is determined as shown in the following table: Table 92 PRIORITY BITS INTERRUPT PRIORITY LEVEL IPxH.x 0 0 1 1 IPx.x 0 1 0 1 Level 0 (lowest priority) Level 1 Level 2 Level 3 (highest priority) The priority scheme for servicing the interrupts is the same as that for the 80C51, except there are four interrupt levels rather than two as on the 80C51. An interrupt will be serviced as long as an interrupt of equal or higher priority is not already being serviced. If an interrupt of equal or higher level priority is being serviced, the new interrupt will wait until it is finished before being serviced. If a lower priority level interrupt is being serviced, it will be stopped and the new interrupt serviced. When the new interrupt is finished, the lower priority level interrupt that was stopped will be completed. 1999 Aug 19 131 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 21.2 21.2.1 Interrupt Enable and Priority Registers INTERRUPT ENABLE REGISTER 0 (IEN0) P8xC591 Logic 0 = interrupt disabled; logic 1 = interrupt enabled. Table 93 Interrupt Enable Register 0 (address A8H) 7 EA 6 EAD 5 ES1 4 ES0 3 ET1 2 EX1 1 ET0 0 EX0 Table 94 Description of IEN0 bits BIT 7 SYMBOL EA DESCRIPTION Global enable/disable control. If bit EA is: LOW, then no interrupt is enabled. HIGH, then any individually enabled interrupt will be accepted. 6 5 4 3 2 1 0 21.2.2 EAD ES1 ES0 ET1 EX1 ET0 EX0 Enable ADC interrupt. Enable SIO1 (I2C) interrupt. Enable SIO0 (UART) interrupt. Enable Timer 1 interrupt. Enable External 1 interrupt / Seconds interrupt. Enable Timer 0 interrupt. Enable External 0 interrupt. INTERRUPT ENABLE REGISTER 1 (IEN1) Logic 0 = interrupt disabled; logic 1 = interrupt enabled. Table 95 Interrupt Enable Register 1 (address E8H) 7 ET2 6 ECAN 5 ECM1 4 ECM0 3 ECT3 2 ECT2 1 ECT1 0 ECT0 Table 96 Description of IEN1 bits BIT 7 6 5 4 3 2 1 0 SYMBOL ET2 ECAN ECM1 ECM0 ECT3 ECT1 ECT1 ECT0 Enable T2 overflow interrupt(s). Enable CAN interrupt. Enable T2 comparator 1 interrupt. Enable T2 comparator 0 interrupt. Enable T2 capture register 3 interrupt. Enable T2 capture register 2 interrupt. Enable T2 capture register 1 interrupt. Enable T2 capture register 0 interrupt. DESCRIPTION 1999 Aug 19 132 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 21.2.3 INTERRUPT PRIORITY REGISTER 0 (IP0) P8xC591 Logic 0 = low priority; logic 1 = high priority. Table 97 Interrupt Priority Register 0 (address B8H) 7 - 6 PAD 5 PS1 4 PS0 3 PT1 2 PX1 1 PT0 0 PX0 Table 98 Description of IP0 bits BIT 7 6 5 4 3 2 1 0 21.2.4 SYMBOL - PAD PS1 PS0 PT1 PX1 PT0 PX0 Reserved for future use. ADC interrupt priority level. SIO1 (I2C) interrupt priority level. SIO0 (UART) interrupt priority level. Timer 1 interrupt priority level. External interrupt 1/Seconds priority level. Timer 0 interrupt priority level. External interrupt 0 priority level. DESCRIPTION INTERRUPT PRIORITY HIGH REGISTER 0 (IP0H) Logic 0 = low priority; logic 1 = high priority. Table 99 Interrupt Priority High Register 0 (address B7H) 7 - 6 PADH 5 PS1H 4 PS0H 3 PT1H 2 PX1H 1 PT0H 0 PX0H Table 100Description of IP0H bits BIT 7 6 5 4 3 2 1 0 SYMBOL - PADH PS1H PS0H PT1H PX1H PT0H PX0H Reserved for future use. ADC interrupt priority level. SIO1 (I2C) interrupt priority level. SIO0 (UART) interrupt priority level. Timer 1 interrupt priority level. External interrupt 1/Seconds priority level. Timer 0 interrupt priority level. External interrupt 0 priority level. DESCRIPTION 1999 Aug 19 133 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 21.2.5 INTERRUPT PRIORITY REGISTER 1 (IP1) P8xC591 Logic 0 = low priority; logic 1 = high priority. Table 101Interrupt Priority Register 1 (address F8H) 7 PT2 6 PCAN 5 PCM1 4 PCM0 3 PCT3 2 PCT2 1 PCT1 0 PCT0 Table 102Description of IP1 bits BIT 7 6 5 4 3 2 1 0 21.2.6 SYMBOL PT2 PCAN PCM1 PCM0 PCT3 PCT2 PCT1 PCT0 CAN interrupt priority level. T2 comparator 1 interrupt priority level. T2 comparator 0 interrupt priority level. T2 capture register 3 interrupt priority level. T2 capture register 2 interrupt priority level. T2 capture register 1 interrupt priority level. T2 capture register 0 interrupt priority level. DESCRIPTION T2 overflow interrupt(s) priority level. INTERRUPT PRIORITY REGISTER HIGH 1 (IP1H) Logic 0 = low priority; logic 1 = high priority. Table 103Interrupt Priority Register High 1 (address F7H) 7 PT2 6 PCANH 5 PCM1H 4 PCM0H 3 PCT3H 2 PCT2H 1 PCT1H 0 PCT0H Table 104Description of IP1H bits BIT 7 6 5 4 3 2 1 0 SYMBOL PT2 PCANH PCM1H PCM0H PCT3H PCT2H PCT1H PCT0H CAN interrupt priority level high. T2 comparator 1 interrupt priority level. T2 comparator 0 interrupt priority level. T2 capture register 3 interrupt priority level. T2 capture register 2 interrupt priority level. T2 capture register 1 interrupt priority level. T2 capture register 0 interrupt priority level. DESCRIPTION T2 overflow interrupt(s) priority level. 1999 Aug 19 134 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 21.3 Interrupt priority 21.4 Interrupt Vectors P8xC591 Table 105 Interrupt priority structure SOURCE External interrupt 0 SIO1 (I2C) ADC completion Timer 0 overflow T2 capture 0 T2 compare 0 External interrupt 1 T2 capture 1 T2 compare 1 Timer 1 overflow T2 capture 2 CAN Serial I/O 0 (UART) T2 compare 3 Timer T2 overflow SYMBOL X0 S1 ADC T0 CT0 CM0 X1 CT1 CM1 T1 CT2 CAN S0 CT3 T2 (lowest) PRIORITY WITHIN LEVEL (highest) The vector indicates the Program Memory location where the appropriate interrupt service routine starts (see Table 106). Table 106 Interrupt vector addresses SOURCE External interrupt 0 Timer 0 overflow External interrupt 1 Timer 1 overflow Serial I/O 0 (UART) SIO1 (I2C) T2 capture 0 T2 capture 1 T2 capture 2 T2 capture 3 ADC completion T2 compare 0 T2 compare 1 CAN interrupt T2 overflow SYMBOL X0 T0 X1 T1 S0 S1 CT0 CT1 CT2 CT3 ADC CM0 CM1 CAN T2 VECTOR 0003H 000BH 0013H 001BH 0023H 002BH 0033H 003BH 0043H 004BH 0053H 005BH 0063H 006BH 0073H 1999 Aug 19 135 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 22 INSTRUCTION SET P8xC591 For the description of the Data Addressing Modes and Hexadecimal opcode cross-reference see Table 111. Table 107 Instruction set description: Arithmetic operations MNEMONIC Arithmetic operations ADD ADD ADD ADD ADDC ADDC ADDC ADDC SUBB SUBB SUBB SUBB INC INC INC INC DEC DEC DEC DEC INC MUL DIV DA A,Rr A,direct A,@Ri A,#data A,Rr A,direct A,@Ri A,#data A,Rr A,direct A,@Ri A,#data A Rr direct @Ri A Rr direct @Ri DPTR AB AB A Add register to A Add direct byte to A Add indirect RAM to A Add immediate data to A Add register to A with carry flag Add direct byte to A with carry flag Add indirect RAM to A with carry flag Add immediate data to A with carry flag Subtract register from A with borrow Subtract direct byte from A with borrow Subtract indirect RAM from A with borrow Subtract immediate data from A with borrow Increment A Increment register Increment direct byte Increment indirect RAM Decrement A Decrement register Decrement direct byte Decrement indirect RAM Increment data pointer Multiply A and B Divide A by B Decimal adjust A 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 4 4 1 2* 25 26, 27 24 3* 35 36, 37 34 9* 95 96, 97 94 04 0* 05 06, 07 14 1* 15 16, 17 A3 A4 84 D4 DESCRIPTION BYTES CYCLES OPCODE (HEX) 1999 Aug 19 136 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller Table 108 Instruction set description: Logic operations MNEMONIC Logic operations ANL ANL ANL ANL ANL ANL ORL ORL ORL ORL ORL ORL XRL XRL XRL XRL XRL XRL CLR CPL RL RLC RR RRC SWAP A,Rr A,direct A,@Ri A,#data direct,A direct,#data A,Rr A,direct A,@Ri A,#data direct,A direct,#data A,Rr A,direct A,@Ri A,#data direct,A direct,#data A A A A A A A AND register to A AND direct byte to A AND indirect RAM to A AND immediate data to A AND A to direct byte AND immediate data to direct byte OR register to A OR direct byte to A OR indirect RAM to A OR immediate data to A OR A to direct byte OR immediate data to direct byte Exclusive-OR register to A Exclusive-OR direct byte to A Exclusive-OR indirect RAM to A Exclusive-OR immediate data to A Exclusive-OR A to direct byte Exclusive-OR immediate data to direct byte Clear A Complement A Rotate A left Rotate A left through the carry flag Rotate A right Rotate A right through the carry flag Swap nibbles within A 1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 2 2 3 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 2 1 1 1 1 1 2 1 1 1 1 1 1 1 DESCRIPTION BYTES CYCLES P8xC591 OPCODE (HEX) 5* 55 56, 57 54 52 53 4* 45 46, 47 44 42 43 6* 65 66, 67 64 62 63 E4 F4 23 33 03 13 C4 1999 Aug 19 137 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller Table 109 Instruction set description: Data transfer MNEMONIC Data transfer MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVC MOVC MOVX MOVX MOVX MOVX PUSH POP XCH XCH XCH XCHD Note 1. MOV A,ACC is not permitted. A,Rr A,@Ri A,#data Rr,A Rr,direct Rr,#data direct,A direct,Rr direct,direct direct,@Ri direct,#data @Ri,A @Ri,direct @Ri,#data DPTR,#data 16 A,@A+DPTR A,@A+PC A,@Ri A,@DPTR @Ri,A @DPTR,A direct direct A,Rr A,direct A,@Ri A,@Ri Move register to A Move indirect RAM to A Move immediate data to A Move A to register Move direct byte to register Move immediate data to register Move A to direct byte Move register to direct byte Move direct byte to direct Move indirect RAM to direct byte Move immediate data to direct byte Move A to indirect RAM Move direct byte to indirect RAM Move immediate data to indirect RAM Load data pointer with a 16-bit constant Move code byte relative to DPTR to A Move code byte relative to PC to A Move external RAM (8-bit address) to A Move external RAM (16-bit address) to A Move A to external RAM (8-bit address) Move A to external RAM (16-bit address) Push direct byte onto stack Pop direct byte from stack Exchange register with A Exchange direct byte with A Exchange indirect RAM with A Exchange LOW-order digit indirect RAM with A 1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 3 1 1 1 1 1 1 2 2 1 2 1 1 1 1 1 1 1 2 1 1 2 2 2 2 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 DESCRIPTION BYTES CYCLES P8xC591 OPCODE (HEX) E* E5 E6, E7 74 F* A* 7* F5 8* 85 86, 87 75 F6, F7 A6, A7 76, 77 90 93 83 E2, E3 E0 F2, F3 F0 C0 D0 C* C5 C6, C7 D6, D7 A,direct (Note 1) Move direct byte to A 1999 Aug 19 138 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller Table 110 Instruction set description: Boolean variable manipulation, Program and machine control MNEMONIC Boolean variable manipulation CLR CLR SETB SETB CPL CPL ANL ANL ORL ORL MOV MOV C bit C bit C bit C,bit C,/bit C,bit C,/bit C,bit bit,C Clear carry flag Clear direct bit Set carry flag Set direct bit Complement carry flag Complement direct bit AND direct bit to carry flag AND complement of direct bit to carry flag OR direct bit to carry flag OR complement of direct bit to carry flag Move direct bit to carry flag Move carry flag to direct bit 1 2 1 2 1 2 2 2 2 2 2 2 1 1 1 1 1 1 2 2 2 2 1 2 DESCRIPTION BYTES CYCLES P8xC591 OPCODE (HEX) C3 C2 D3 D2 B3 B2 82 B0 72 A0 A2 92 *1 12 22 32 1 02 80 73 60 70 40 50 20 30 10 B5 B4 B* B6, B7 D* D5 00 Program and machine control ACALL LCALL RET RETI AJMP LJMP SJMP JMP JZ JNZ JC JNC JB JNB JBC CJNE CJNE CJNE CJNE DJNZ DJNZ NOP addr11 addr16 rel @A+DPTR rel rel rel rel bit,rel bit,rel bit,rel A,direct,rel A,#data,rel Rr,#data,rel Rr,rel direct,rel addr11 addr16 Absolute subroutine call Long subroutine call Return from subroutine Return from interrupt Absolute jump Long jump Short jump (relative address) Jump indirect relative to the DPTR Jump if A is zero Jump if A is not zero Jump if carry flag is set Jump if carry flag is not set Jump if direct bit is set Jump if direct bit is not set Jump if direct bit is set and clear bit Compare direct to A and jump if not equal Compare immediate to A and jump if not equal Compare immediate to register and jump if not equal Decrement register and jump if not zero Decrement direct and jump if not zero No operation 2 3 1 1 2 3 2 1 2 2 2 2 3 3 3 3 3 3 3 2 3 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 @Ri,#data,rel Compare immediate to indirect and jump if not equal 1999 Aug 19 139 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller Table 111 Description of the mnemonics in the Instruction set MNEMONIC Data addressing modes Rr direct @Ri #data #data 16 bit addr16 addr11 rel Working register R0-R7. 128 internal RAM locations and any special function register (SFR). DESCRIPTION P8xC591 Indirect internal RAM location addressed by register R0 or R1 of the actual register bank. 8-bit constant included in instruction. 16-bit constant included as bytes 2 and 3 of instruction. Direct addressed bit in internal RAM or SFR. 16-bit destination address. Used by LCALL and LJMP. The branch will be anywhere within the 64 kbytes Program Memory address space. 11-bit destination address. Used by ACALL and AJMP. The branch will be within the same 2 kbytes page of Program Memory as the first byte of the following instruction. Signed (two's complement) 8-bit offset byte. Used by SJMP and all conditional jumps. Range is -128 to +127 bytes relative to first byte of the following instruction. Hexadecimal opcode cross-reference * * 8, 9, A, B, C, D, E, F. 1, 3, 5, 7, 9, B, D, F. 0, 2, 4, 6, 8, A, C, E. * Immediate Addressing - Program Memory (in-code 8 bit or 16 bit constant) * Base-Register-plus-Index-Register-Indirect Addressing - Program Memory look-up table (@DPTR+A, @PC+A) The first three addressing modes are usable for destination operands. 22.1 Addressing Modes Most instructions have a `destination, source' field that specifies the data type, addressing modes and operands involved. For all these instructions, except for MOVs, the destination operand is also the source operand (e.g. ADD A,R7). There are five kinds of addressing modes: * Register Addressing - R0 - R7 (4 banks) - A,B,C (bit), AB (2 bytes), DPTR (double byte) * Direct Addressing - lower 128 bytes of internal Main RAM (including the 4 R0-R7 register banks) - Special Function Registers - 128 bits in a subset of the internal Main RAM - 128 bits in a subset of the Special Function Registers * Register-Indirect Addressing - internal Main RAM (@R0, @R1, @SP [PUSH/POP]) - internal Auxiliary RAM (@R0, @R1, @DPTR) - external Data Memory (@R0, @R1, @DPTR) 1999 Aug 19 140 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 23 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); Note 1 SYMBOL VDD VI II, IO Ptot Tstg Tamb VPP Notes 1. The following applies to the Absolute Maximum Ratings: PARAMETER Voltage on VDD to VSS and SCL, SDA to VSS Input voltage on any other pin to VSS Input/output current on any I/O pin Total power dissipation (Note 2) Storage temperature range Operating ambient temperature range: P8xC591SFx Voltage on EA/VPP to VSS -40 -0.5 +85 +13 MIN. -0.5 -0.5 - - -65 MAX. +6.5 P8xC591 UNIT V V mA W C C V VDD + 0.5 5 1.0 +150 a) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the Chapters 24 and 25 of this specification is not implied. b) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effect of excessive static charge. However, its suggested that conventional precautions be taken to avoid applying greater than the rated maxima. c) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. 2. This value is based on the maximum allowable die temperature and the thermal resistance of the package, not on device power consumption. 1999 Aug 19 141 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 24 DC CHARACTERISTICS (VALUES IN THIS TABLE NOT CONFIRMED) VDD = 5 V 10%; VSS = 0 V; all voltages with respect to VSS unless otherwise specified; Tamb = -40 to +85 C for the P8xC591SFx; VDD = 5 V 10%; VSS = 0 V; AVSS = 0 V. SYMBOL Supply IDD IID IPD Inputs VIL VIL1 VIL2 VIL3 VIH VIH1 VIH2 VIH3 IIL LOW level input voltage (except P1.0, P1.1, P1.6, P1.7) LOW level input voltage EA LOW level input voltage P1.0 and P1.1 LOW level input voltage P1.6 and P1.7 HIGH level input voltage (except P1.0, P1.1, P1.6, P1.7, XTAL1, RST) HIGH level input voltage XTAL1, RST HIGH level input voltage P1.6 and P1.7 HIGH level input voltage P1.0 and P1.1 LOW level input current Ports 1, 2, and 3 VIN = 0.45 V in pseudo-bidirectional output mode (except P1.6, P1.7) input current HIGH-to-LOW transition Ports 1, 2, 3 in pseudo-bidirectional output mode (except P1.6, P1.7) input leakage current, Ports 0, 2, 3 and P1.0, P1.1 in high impedance configurations input leakage current, Port 1 (except P1.0, P1.1) 0.45 V < VIN < VDD see Note 6 see Note 6 -0.5 -0.5 -0.5 operating supply current supply current Idle mode supply current Power-down mode tCLK = 16 MHz; see Notes 2 and 3 tCLK = 16 MHz see Notes 2 and 4 2 V < VPD < VDD; see Notes 2 and 5 - 45 25 PARAMETER CONDITIONS MIN. P8xC591 MAX. UNIT mA mA A 100 0.2 VDD - 0.1 0.2 VDD - 0.3 0.2 VDD 0.3 VDD V V V V V V V V A 0.2 VDD + 0.9 VDD + 0.5 0.7 VDD 0.7 VDD 0.8 VDD -1 VDD + 0.5 6 VDD -50 ITL -650 A IIL1 10 A IIL2 0.45 V < VIN < VDD 1 A 1999 Aug 19 142 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 SYMBOL Outputs VOL VOL1 VOL2 VOL3 VOH PARAMETER CONDITIONS MIN. MAX. UNIT LOW level output voltage Ports 1, 2, 3 (except P1.0, P1.6, P1.7) LOW level output voltage Port 0, ALE, PSEN, RST, PWM0, PWM1 LOW level output voltage P1.6, P1.7 LOW level output voltage P1.0 and P1.1 IOL = 1.6 mA; see Note 8 IOL = 3.2; see Note 8 IOL = 3.0 mA; see Note 8 IOL = 8.0 mA - - 2.4 0.4 0.4 0.4 0.3 VDD V V V V V HIGH level output voltage Ports 1, 2, 3 in IOH = -60 A pseudo-bidirectional output mode (except P1.1, P1.6 and P1.7 HIGH level output voltage Port 0 and Port 2 in external bus mode, Port 2 in push-pull mode, ALE, PSEN, PWM0, PWM1 IOH = -3.2 mA; see Note 9 VOH1 VDD -0.7 V VOH2 VOH3 HIGH level output voltage, P1.0 and P1.1 IOH = -1.6 mA HIGH level output voltage, Ports 1, 2, 3 in IOH = -1.6 mA push-pull output mode (except P1.0, P1.1, P1.6, P1.7) RST pull-up resistor I/O pin capacitance test frequency = 1 MHz; Tamb = 25 C 0.7 VDD VDD -0.7 V V RRST CI/O 40 - 225 15 k pF Analog inputs AVIN AVref+ RREF CIA tADS tADC DLe ILe8 ILe OSe8 OSe Ge Ae Mctc Ct analog input voltage reference voltage resistance between AVref+ and AVSS analog input capacitance sampling time conversion time (including sampling time) differential non-linearity integral non-linearity (8-bit mode) integral non-linearity offset error (8-bit mode) offset error gain error absolute voltage error channel-to-channel matching crosstalk between analog inputs of Port 1 0 to 100 kHz; see Notes 17, 18 see Notes 10, 16 see Notes 10, 15 see Notes 10, 13 see Notes 10, 11, 12 AVSS - 0.2 - 10 - - - - - - - - - - - - VDD + 0.2 VDD + 0.2 50 15 5 tcy; Note 1 8 tcy V V k pF s s 24 tcy; Note 1 s 50 tcy s 1 1; Note 1 2 1; Note 1 2 0.4 3 1 -60 LSB LSB LSB LSB LSB % LSB LSB dB 1999 Aug 19 143 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller Notes to the DC characteristics 1. 8-bit mode 2. See Figures 62 through 66 for IDD test conditions. P8xC591 3. The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10 ns; VIL = VSS + 0.5 V; VIH = VDD - 0.5 V; XTAL2 not connected; EA = RST = Port 0 = VDD. 4. The Idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10 ns; VIL = VSS + 0.5 V; VIH = VDD - 0.5 V; XTAL2 not connected; Port 0 = VDD; EA = RST = VSS. 5. The Power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = VDD; EA = RST = XTAL1 = VSS. 6. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I2C specification, so an input voltage below 1.5 V will be recognized as a logic 0 while an input voltage above 3.0 V will be recognized as a logic 1. 7. Pins of Port 1 (except P1.6, P1.7), 2 and 3 source a transition current when they are being externally driven from HIGH to LOW. The transition current reaches its maximum value when VIN is approximately 2 V. 8. Capacitive loading on Ports 0 and 2 may cause spurious noise to be superimposed on the VOL of ALE and Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make HIGH-to-LOW transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no single outputs sinks more than 5 mA and no more than two outputs exceed in the test conditions. 9. Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9 VDD specification when the address bits are stabilizing. 10. Conditions: AVSS = 0 V; VDD = 5.0 V. Measurement by continuous conversion of AVIN = -20 mV to 5.12 V in steps of 0.5 mV, derivating parameters from collected conversion results of ADC. AVREF+ (P8xC591) = 4.977 V, ADC is monotonic with not missing codes. 11. The differential non-linearity (DLe) is the difference between the actual step width and the ideal step width (see Fig.54). 12. The ADC is monotonic; there are no missing codes. 13. The integral non-linearity (ILe) is the peak difference between the centre of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset error (see Fig.54). 14. The offset error (OSe) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and a straight line which fits the ideal transfer curve (see Fig.54). 15. The gain error (Ge) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset error), and the straight line which fits the ideal transfer curve. Gain error is constant at every point on the transfer curve (see Fig.54). 16. The absolute voltage error (Ae) is the maximum difference between the centre of the steps of the actual transfer curve of the non-calibrated ADC and the ideal transfer curve. 17. This should be considered when both analog and digital signals are simultaneously input to Port 1. 18. The parameter is guaranteed by design and characterized, but is not production tested. 1999 Aug 19 144 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 dbook, full pagewidth offset error OSe 1023 1022 1021 1020 1019 1018 gain error Ge (2) code out 7 (1) 6 5 4 (5) (4) 3 2 1 0 (3) 1 LSB (ideal) 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 Vin(A) (LSBideal) offset error OS e 1LSB ideal AV REF+ = ------------------1024 MGD634 (1) (2) (3) (4) (5) Example of an actual transfer curve. The ideal transfer curve. Differential non-linearity (DLe). Integral non-linearity (ILe). Centre of a step of the actual transfer curve. Fig.54 ADC conversion characteristic. 1999 Aug 19 145 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 25 AC CHARACTERISTICS VDD = 5 V 10%; VSS = 0 V; Tamb = -40 C to +85C; CL = 100 pF for Port 0, ALE and PSEN; CL = 80 pF for all other outputs unless otherwise specified. 16 MHz CLOCK SYMBOL PARAMETER MIN. External Program Memory; see Fig.55 1/fCLK tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tWHQX tQVWH tRLAZ tWHLH tCHCX tCLCX tCLCH tCHCL System clock frequency; see Note 1 ALE pulse width address valid to ALE LOW address hold after ALE LOW ALE LOW to valid instruction in ALE LOW to PSEN LOW PSEN pulse width PSEN LOW to valid instruction in input instruction hold after PSEN input instruction float after PSEN address to valid instruction in PSEN LOW to address float 22 6 6 - 6 48 - 0 - - - - - - 60 - - 33 - 6 76 10 - - 66 - 34 100 116 143 - - - - 0 56 3.5 0.5 tCLK - 25 0.5 tCLK - 25 0.5 tCLK - 25 - 0.5 tCLK - 25 1.5 tCLK - 45 - 0 - - - 3 tCLK - 100 3 tCLK - 100 - 0 - - - 1.5 tCLK - 50 2 tCLK - 75 0.5 tCLK - 30 0.5 tCLK - 25 3.5 tCLK - 130 - 0.5 tCLK - 25 tCLK x 0.4 tCLK x 0.4 - - 16 - - - 2 tCLK - 65 - - 1.5 tCLK - 60 - 0.5 tCLK - 25 2.5 tCLK - 80 10 - - 2.5 tCLK - 90 - 2 tCLK - 28 4 tCLK - 150 1.5 tCLK + 50 - - - - 0 0.5 tCLK + 25 tCLK x 0.6 tCLK x 0.6 20 20 MHz ns ns ns ns ns ns ns ns ns ns ns MAX. MIN. MAX. VARIABLE CLOCK UNIT External Data Memory; see Fig.56 and Fig.57 RD pulse width WR pulse width RD LOW to valid data in data hold after RD data float after RD ALE LOW to valid data in address to valid data in ALE LOW to RD or WR LOW address valid to RD or WR LOW data valid to WR transition data hold after WR data valid time WR HIGH RD LOW to address float RD or WR HIGH to ALE HIGH 87 87 - 0 - - - 43 50 0 6 88 - 6 ns ns ns ns ns ns ns ns ns ns ns ns ns 4.5 tCLK - 165 ns External Clock; see Fig.65 high time low time rise time fall time tCLK x 0.4 tCLK x 0.6 tCLK x 0.4 tCLK x 0.6 - - 20 20 ns ns ns ns 1999 Aug 19 146 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 16 MHz CLOCK SYMBOL PARAMETER MIN. UART Timing - Shift Register Mode; see Fig.59 tXLXL tQVXH tXHQX tXHDX tXHDV Note 1. Parts a guaranteed to operate down to 0 Hz. Table 112 I2C-bus interface timing All values referred to VIH(min) and VIL(max) levels; see Fig.61. serial port clock cycle time output data setup to clock rising edge output data hold after clock rising edge input data hold after clock rising edge clock rising edge to input data valid 375 180 50 0 - - - - - 176 MAX. VARIABLE CLOCK MIN. MAX. - - - - 5 tCLK-133 UNIT 6 tCLK 5 tCLK - 133 tCLK-10 0 - ns ns ns ns ns I2C-BUS SYMBOL tHD;STA tLOW tHIGH tRC tFC tSU;DAT1 tSU;DAT2 tSU;DAT3 tHD;DAT tSU;STA tSU;STO tBUF tRD tFD Notes 1. At 100 kbit/s. At other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s. 2. Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1 s. 3. Spikes on the SDA and SCL lines with a duration of less than 3 tCLK will be filtered out. Maximum capacitance on bus-lines SDA and SCL = 400 pF. 4. tCLK = 1/fCLK = one oscillator clock period at pin XTAL1. For 62 ns < tCLK < 285 ns (8 MHz > fCLK > 3.5 MHz) the SI01 interface meets the I2C-bus specification for bit-rates up to 100 kbit/s. 5. These values are guaranteed but not 100% production tested. PARAMETER INPUT START condition hold time LOW period of the SCL clock HIGH period of the SCL clock rise time of SCL signals fall time of SCL signals data set-up time SDA set-up time (before repeated START condition) SDA set-up time (before STOP condition) data hold time set-up time for a repeated START condition set-up time for STOP condition bus free time between rise time of SDA signals fall time of SDA signals 14 tCLK 16 tCLK 14 tCLK 1 s 0.3 s 250 ns 250 ns 250 ns 0 ns 14 tCLK 14 tCLK 14 tCLK 1 s 0.3 s OUTPUT > 4.0 s(1) > 4.7 s(1) > 4.0 s(1) - (2) < 3.0 s(3) > 20 tCLK - tRD > 1 s(1) > 8 tCLK > 8 tCLK - tFC > 4.7 s(1) > 4.0 s(1) > 4.7 s(1) - (2) < 0.3 s(3) 1999 Aug 19 147 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 handbook, full pagewidth t LHLL ALE t LLPL t AVLL t LLIV t PLIV PSEN t LLAX t PLAZ PORT 0 A0 - A7 t AVIV t PXIX INSTR IN A0 - A7 t PXIZ t PLPH PORT 2 A8 - A15 A8 - A15 MBC483 - 1 Fig.55 External program memory read cycle. 1999 Aug 19 148 Philips Semiconductors handbook, full pagewidth 1999 Aug 19 t WHLH t LLDV t LLWL t RLRH t LLAX t RLDV t RHDX DATA IN A0 - A7 from PCL INSTR IN t RHDZ ALE PSEN RD Single-chip 8-bit microcontroller with CAN controller 149 t AVWL t AVDV P2.0 - P2.7 or A8 - A15 from DPH t AVLL PORT 0 A0 - A7 from RI or DPL PORT 2 A8 - A15 from PCH MBC485 - 1 Objective Specification P8xC591 Fig.56 External data memory read cycle. Philips Semiconductors handbook, full pagewidth 1999 Aug 19 t WHLH t LLWL t WLWH ALE PSEN Single-chip 8-bit microcontroller with CAN controller 150 t QVWX t AVLL t QVWH DATA OUT A0 - A7 from RI or DPL t AVWL P2.0 - P2.7 or A8 - A15 from DPH t LLAX t WHQX WR PORT 0 A0 - A7 from PCL INSTR IN PORT 2 A8 - A15 from PCH MBC486 - 1 Objective Specification P8xC591 Fig.57 External data memory write cycle. Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 handbook, full pagewidth t HIGH V IH1 0.8 V V IH1 0.8 V t LOW tr V IH1 0.8 V V IH1 tf 0.8 V t CLK MGA175 Fig.58 External clock drive XTAL1. INSTRUCTION handbook, full pagewidth 0 1 2 3 4 5 6 7 8 ALE t XLXL CLOCK t XHQX t QVXH OUTPUT DATA t XHDX WRITE TO SBUF INPUT DATA t XHDV VALID VALID VALID VALID VALID VALID VALID SET TI VALID CLEAR RI MBC475 SET RI Fig.59 Shift register mode timing waveforms. 1999 Aug 19 151 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 handbook, full pagewidth 2.4 V test points 2.0 V 0.8 V 0.45 V (a) float 2.4 V 2.0 V 0.8 V 2.0 V 0.8 V 2.4 V 0.45 V 0.45 V MGA174 (b) AC testing inputs are driven at 2.4 V for a HIGH and 0.45 V for a LOW. Timing measurements are taken at 2.0 V for a HIGH and 0.8 V for a LOW, see Fig.60 (a). The float state is defined as the point at which a Port 0 pin sinks 3.2 mA or sources 400 A at the voltage test levels, see Fig.60 (b). Fig.60 AC testing input, output waveform (a) and float waveform (b). 1999 Aug 19 152 Philips Semiconductors handbook, full pagewidth 1999 Aug 19 repeated START condition START condition STOP condition t RD t SU;STA 0.7 V DD 0.3 VDD t FC t BUF t SU;STO 0.7 VDD 0.3 VDD t SU;DAT3 t SU;DAT2 MBC482 START or repeated START condition SDA (input / output) Single-chip 8-bit microcontroller with CAN controller t FD t RC 153 t HIGH t SU;DAT1 t HD;DAT SCL (input / output) t HD;STA t LOW Objective Specification P8xC591 Fig.61 I2C interface timing. Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 FIGURE IS IN PREPARATION ! Fig.62 IDD as a function of frequency. handbook, full pagewidth VDD VDD IDD P1.6 P1.7 RST P0 VDD VDD (n.c.) CLOCK SIGNAL XTAL2 XTAL1 VSS P8xC591 EA AVSS MHI056 All other pins are disconnected. (1) The following pins must be forced to VDD: EA and Port 0. (2) The following pins must be forced to VSS: AVSS and RST. (3) Port 1.6 and 1.7 should be connected to VDD through resistors of sufficiently high value such that the sink current into these pins cannot exceed the IOL1 spec of the pins. (4) The following pins must be disconnected: XTAL2 and all pins not specified above. Fig.63 IDD Test Conditions, Active Mode. 1999 Aug 19 154 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 handbook, full pagewidth VDD VDD IDD P1.6 P1.7 RST P0 VDD VDD (n.c.) CLOCK SIGNAL XTAL2 XTAL1 VSS P8xC591 EA AVSS MHI057 All other pins are disconnected. (1) The following pins must be forced to VDD: Port 0 and RST. (2) The following pins must be forced to VSS: AVSS and EA. (3) Port 1.6 and 1.7 should be connected to VDD through resistors of sufficiently high value such that the sink current into these pins cannot exceed the IOL1 spec of the pins. These pins must not have logic 0 written to them prior to this measurement. (4) The following pins must be disconnected: XTAL2 and all pins not specified above. Fig.64 IDD Test Condition, Idle Mode. handbook, full pagewidth VDD-0.5 0.7 VDD 0.2 VDD-0.1 0.5 V tCHCL tCLCX tCLK tCHCX tCHCL MHI058 Fig.65 Clock Signal Waveform for IDD Tests in Active and Idle Modes tCLCH = tCHCL = 10 ns. 1999 Aug 19 155 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller P8xC591 handbook, full pagewidth VDD VDD IDD P1.6 P1.7 RST P0 VDD VDD (n.c.) CLOCK SIGNAL XTAL2 XTAL1 VSS P8xC591 EA AVSS MHI057 All other pins are disconnected. VDD = 2 V to 5.5 V (1) The following pins must be forced to VDD: Port 0 and RST. (2) The following pins must be forced to VSS: AVSS and EA. (3) Port 1.6 and 1.7 should be connected to VDD through resistors of sufficiently high value such that the sink current into these pins cannot exceed the IOL1 spec of the pins. These pins must not have logic 0 written to them prior to this measurement. (4) The following pins must be disconnected: XTAL2 and all pins not specified above. Fig.66 IDD Test Condition, Power-down Mode. 1999 Aug 19 156 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 25.1 Timing symbol definitions 26 EPROM CHARACTERISTICS P8xC591 Oscillator: fCLK = clock frequency tCLK = clock period Timing symbols (acronyms): Each timing symbol has five characters. The first character is always a 't' (= time). the remaining four characters of the symbol (typed in subscript), depending on their relative positions, indicate the name of a signal or the logical status of that signal. the designations are as follows: The P8xC591 contains three signature bytes that can be read and used by an EPROM programming system to identify the device. The signature bytes identify the device as an P8xC591 manufactured by Philips: * (030H) = 15H indicates manufactured by Philips * (0031H) = 98H indicates Hamburg * (60H) = 01H indicates P87C591 26.1 Program verification A =address C = clock D = input data H = logic level HIGH I = instruction (program memory contents) L = Logic level LOW or ALE P = PSEN Q = output data R = RD signal t = time V = valid W = WR signal X = no longer a valid logic level Z = float Examples: If security bits 2 or 3 have not been programmed, the on-chip program memory can be read out for program verification. If the encryption table has been programmed, the data presented at port 0 will be exclusive NOR of the program byte with one of the encryption bytes. The user will have to know the encryption table contents in order to correctly decode the verification data. The encryption table itself cannot be read out. 26.2 Security bits tAVLL = time for address valid to ALE LOW tLLPL = time for ALE LOW to PSEN LOW With none of the security bits programmed the code in the program memory can be verified. If the encryption table is programmed, the code will be encrypted when verified. When only security bit 1 (see Table 113) is programmed, MOVC instructions executed from external program memory are disabled from fetching code bytes from the internal memory. EA is latched on Reset and all further programming of the EPROM is disabled. When security bits 1 and 2 are programmed, in addition to the above, verify mode is disabled. When all three security bits are programmed, all of the conditions above apply and all external program memory execution is disabled. Table 113 Program security bits for EPROM devices P = programmed; U = unprogrammed. PROGRAM LOCK BITS(1) 1 2 SB1 SB2 SB3 U P U U U U PROTECTION DESCRIPTION No Program Security features enabled. (Code verify will still be encrypted by the Encryption Array if programmed.). MOVC instructions executed from external Program Memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on reset, and further programming of the EPROM is disabled. Same as 2, also verify is disabled. Same as 3, and external memory execution is disabled. 3 4 Note P P P P U P 1. Any other combination of the security bits is not defined. 1999 Aug 19 157 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 27 PACKAGE OUTLINES PLCC44: plastic leaded chip carrier; 44 leads P8xC591 SOT187-2 eD y X A ZE eE 39 29 28 bp 40 b1 wM 44 HE A e A4 A1 (A 3) k 7 e D HD 17 ZD B vMB vM A 6 18 k 1 Lp detail X 1 pin 1 index E 0 5 scale 10 mm DIMENSIONS (millimetre dimensions are derived from the original inch dimensions) UNIT mm A 4.57 4.19 A1 min. 0.51 A3 0.25 A4 max. 3.05 bp 0.53 0.33 b1 0.81 0.66 D (1) E (1) e eD eE HD HE k k1 max. 0.51 Lp 1.44 1.02 v 0.18 w 0.18 y 0.10 Z D(1) Z E (1) max. max. 2.16 2.16 16.66 16.66 16.00 16.00 17.65 17.65 1.22 1.27 16.51 16.51 14.99 14.99 17.40 17.40 1.07 45 o 0.180 inches 0.020 0.01 0.165 0.630 0.630 0.695 0.695 0.048 0.057 0.021 0.032 0.656 0.656 0.020 0.05 0.007 0.007 0.004 0.085 0.085 0.12 0.590 0.590 0.685 0.685 0.042 0.040 0.013 0.026 0.650 0.650 Note 1. Plastic or metal protrusions of 0.01 inches maximum per side are not included. OUTLINE VERSION SOT187-2 REFERENCES IEC 112E10 JEDEC MO-047AC EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-25 97-12-16 1999 Aug 19 158 Philips Semiconductors Objective specification Single-chip 8-bit microcontroller with CAN controller P8xC591 QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2 1999 Aug 19 159 Philips Semiconductors Objective Specification Single-chip 8-bit microcontroller with CAN controller 28 SOLDERING 28.1 28.1.1 Plastic leaded-chip carriers/quad flat-packs BY WAVE P8xC591 During placement and before soldering, the component must be fixed with a droplet of adhesive. After curing the adhesive, the component can be soldered. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 C within 6 s. Typical dwell time is 4 s at 250 C. A modified wave soldering technique is recommended using two solder waves (dual-wave), in which a turbulent wave with high upward pressure is followed by a smooth laminar wave. Using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications. 28.1.2 BY SOLDER PASTE REFLOW Several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. Dwell times vary between 50 and 300 s according to method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 min at 45 C. 28.1.3 REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING IRON OR PULSE-HEATED SOLDER TOOL) Fix the component by first soldering two, diagonally opposite, end pins. Apply the heating tool to the flat part of the pin only. Contact time must be limited to 10 s at up to 300 C. When using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 C. (Pulse-heated soldering is not recommended for SO packages. For pulse-heated solder tool (resistance) soldering of VSO packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement. Reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement. 29 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 30 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. 1999 Aug 19 160 Philips Semiconductors Objective specification Single-chip 8-bit microcontroller with CAN controller P8xC591 Data sheet status Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Production [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1999 All rights reserved. Printed in U.S.A. Date of release: 09-99 Document order number: 9397 750 06433 Philips Semiconductors 1999 Aug 19 160 |
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